A Common-Gate Amplifier With Transconductance Nonlinearity Cancellation and Its High-Frequency Analysis Using the Volterra Series

A common-gate (CG) amplifier employing a transconductance nonlinearity cancellation technique is designed for transmitter circuitry. The major contributor to the third-order nonlinearity in the CG amplifier is the second derivative of the transconductor $({ g}_{ m}^{primeprime})$, which is the same case with a common-source (CS) amplifier. The multiple gated transistor (MGTR) technique, which was developed in the CS amplifier for transconductor nonlinearity cancellation, is applied to a CG amplifier. However, in the CG amplifier, the input driving impedance of a CG amplifier comprises a voltage–current feedback loop. Thus, a second-order interaction with feedback components generates a third-order distortion that limits input-referred third-order intercept point (IIP3) enhancement. This feedback influence on IIP3 can be relaxed by eliminating harmonic feedback components. Based on high-frequency analysis on a CG amplifier using the Volterra series, an RF current source is proposed to replace the conventional current source in the CG amplifier to eliminate harmonic feedback components at $2omega$ and $Deltaomega$. By adapting the CG MGTR technique combined with the RF current source, a 2.4-GHz driver amplifier for Wibro/Wimax applications was implemented using a 0.18-$mu{hbox{m}}$ 1P 6M CMOS process. Measurement results show a 9-dB output third-order intercept point improvement at an output power of $-$3 dBm.      

A Robust High-Throughput Tree Algorithm Using Successive Interference Cancellation

A novel random access protocol combining a tree algorithm (TA) with successive interference cancellation (SIC) has been introduced recently. To mitigate the deadlock problem of SICTA arising in error-prone wireless networks, we put forth a SICTA with first success (SICTA/FS) protocol, which is capable of high throughput while requiring limited-sensing and gaining robustness to errors relative to SICTA.     

Acoustic Echo Cancellation Using a Pseudocoherence Function in the Presence of Memoryless Nonlinearity

Acoustic echo cancellation (AEC) is critical for telecommunication applications involving two or more locations such as teleconferencing. It is also challenging because of loudspeaker's nonlinearity, real-time implementation requirement, and multipath effects of indoor environments. This paper addresses the nonlinear AEC problem. We use a Hammerstein model to describe the memoryless nonlinearity of loudspeaker concatenated with a linear room impulse response. We propose a method using a pseudo magnitude squared coherence (MSC) function to identify the nonlinearity in the Hammerstein system and develop an on-line AEC algorithm. Our method identifies nonlinearity without knowing the linear block in the Hammerstein system, which guarantees the stability of the algorithm and leads to a faster convergence rate. Moreover, several alternative criteria based on the MSC function are also proposed for nonlinearity identification. Effectiveness of the proposed algorithms is demonstrated through computer simulations.      

Interference Cancellation for High-Frequency Surface Wave Radar

The performance of high-frequency surface wave radar (HFSWR) is known to suffer from external environmental interference and noise, such as cochannel radio-frequency interference from other radiating source, ionospheric clutter, lightning impulsive noise, etc. This paper experimentally evaluates the interference cancellation performance of various adaptive beamforming schemes with respect to the aforementioned three types of interferences in an attempt to find the most promising adaptive cancellation scheme in practical HFSWR environment.     

Linearly Tunable Transconductor Using Modified CDBA

With a slight modification in current differencing buffered amplifier (CDBA), a new block, namely differential-input current feedback amplifier (DFCA), is obtained. It is shown that, with two additional MOSFETs, this modified CDBA structure can be utilized as a linearly tunable transconductor, which can also be converted to a variable-gain amplifier or an analogue multiplier.     

Averaging and Cancellation Effect of High-Order Nonlinearity of a Power Amplifier

Nonlinear distortion of a power amplifier (PA) due to the nonlinear input-output transfer function is studied. The high-order nonlinearity or Fourier components of the output, due to the mixing of input signals, are found to be related to an average integral related to the transfer function, thus giving insight to the cancellation effect of the nonlinearity. A simple formula has been derived to relate the nth-order Fourier component of a nonlinear transfer function with a sinusoidal input to an average integral of the nth-order derivative of the transfer function. The large signal nonlinear distortion of the nth-order can therefore be regarded as a weighted average of the nth-order derivative of the transfer function. For PAs, the averaging effect gives rise to local minima in the intermodulation distortion terms during power sweep because of the cancellation of the positive part and the negative part of the derivative during averaging. We have applied the formula to InGaP heterojunction bipolar transistors PAs and are able to explain most of the observed nonlinear phenomena of the amplifiers.     

一种可调高线性度跨导器

本文提出了一种新的跨导器结构,它采用CMOS复合对管实现,可以通过调节栅极电压改变跨导器的跨导值,适合应用于高线性的连续时间滤波器.仿真结果表明,在供电电压为5伏,输入差分信号峰峰值为2.3伏的情况下,可以达到小于0.5%的总谐波失真.     

一种零陷展宽稳健旁瓣相消算法

受到实际条件的限制,自适应旁瓣相消器通常不可能频繁地更新自适应权值,使得其在对抗空域非平稳干扰时,会出现权值失配现象,严重影响干扰抑制性能。该文从空域密集干扰产生宽零陷的角度出发,提出一种适用于自适应旁瓣相消器的零陷展宽算法。该算法通过对主通道的合成权值和辅助天线间的协方差矩阵同时进行锥削实现零陷展宽,锥削向量和锥削矩阵只与阵元位置和展宽宽度有关,可以离线计算,在线直接调用,实现简单,适合工程实际使用。仿真实验证明,该文方法可以有效展宽自适应零陷,增强自适应旁瓣相消器对抗空域非平稳干扰时的稳健性。     

一种基于开关跨导混频器的相位插值器

提出一种新型的四路正交混频器,基于该正交混频器设计了一种四路正交相位插值器。在TSMC 40 nm CMOS工艺下的仿真结果表明,在相同的电源电压和仿真环境下,设计的相位插值器与传统结构相比,其步长、积分非线性和微分非线性等指标相近,其中混频器的功耗降低9.5%。在性能相近的条件下,设计的相位插值器的功耗优于传统结构。在更低的电源电压下,基于该混频器的相位插值器将有更好的应用前景。     

A Modified CMOS Balanced Output Transconductor with Extended Linearity

A new CMOS balanced output transconductor is presented. The circuit is based on applying the dynamic biasing technique on the floating current source to extend its linearity range. The difference in the biasing currents is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for high frequency applications requiring a wide dynamic range. Rail-to-rail operation is achieved with THD of –33.64 dB. The bandwidth achieved by the transconductor is 240 MHz, and the supply voltage used is ±1.5 V.     

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

A fully integrated direct conversion DVB-H tuner is realized in a 0.5-mum SiGe BiCMOS technology. To meet the stringent linearity requirement while keeping low power consumption, novel linearization techniques for a variable-gain low-noise amplifier (VG-LNA) and a mixer are proposed. The proposed linearized VG-LNA has a variable gain range of over 50 dB, noise figure of less than 2.6 dB over the frequency range from 200 to 1000 MHz, and IIP3 of more than -10 dBm at a current consumption of 2.1 mA. The quadrature mixer with the proposed linearization technique achieves OIP3 of more than 25 dBm at a current consumption of 5 mA. In addition, a new offset-cancel feedback is introduced for the baseband block of a direct conversion receiver, which keeps the high-pass cutoff frequency independent of the baseband VGA gain. The fabricated tuner IC satisfies all the DVB-H requirements at a power consumption of 184 mW     

A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

The present paper introduces a resonant clock generation and distribution scheme that uses uniform amplitude and uniform phase standing wave oscillators in order to distribute a high-frequency clock signal with low skew, low jitter, and low power. A suitable distributed resonator for a global clock distribution that is inductively loaded transmission line generating a uniform amplitude and uniform phase standing wave is realized through detailed analysis of a standing wave on a loaded transmission line. A test chip is fabricated using 0.18-mum 6 M CMOS technology, and a cascaded distribution network is implemented for a global clock distribution with a space-filling curve. Furthermore, distributed local LC tanks are implemented as local resonant clock networks, which are composed of parasitic capacitors and small spiral inductors. The distributed local LC tanks are driven by a fine clock distributed with cascaded standing-wave oscillators and reduce the primary power in the clock distribution, which is dissipated as dynamic power in the parasitic capacitance of latches and/or flip flops. The measurement results reveal that, at 9.4 GHz, the peak-to-peak jitter is 5.2 ps and the clock skew is 0.8 ps, and the global and local distributions dissipated only 17% and 23% of CV² f power, respectively.     

A Single-Channel Acoustic Echo Cancellation Scheme Using Gradient-Based Adaptive Filtering

In this paper, a single-channel acoustic echo cancellation (AEC) scheme is proposed using a gradient-based adaptive least mean squares (LMS) algorithm. Unlike the conventional dual-channel problem, by considering a delayed version of the echo-suppressed signal as a reference, a modified objective function is formulated and thereby an LMS update equation is derived. It is shown that the resulting update equation converges to the optimum Wiener–Hopf solution. Based on the commonly used assumption of negligibility of cross correlation between the reference and the current speech signals, a multi-step stopping criterion is introduced, which not only provides efficient control of the LMS update sequence but also ensures a faster convergence. The proposed control criterion is validated by considering all possible scenarios which arise due to the variation of speech properties at the reference and current samples of the adaptive filter. From extensive experimentation on several real-life echo-corrupted speech signals in different acoustic environments, it is found that the proposed algorithm can efficiently handle the problem of single-channel AEC and provide satisfactory performance in terms of both subjective and objective measures.     

A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifier's architecture. The offset voltage of a single-stage folded cascode amplifier has been programmed to a minimum of plusmn25 muV in a 0.5 mum digital CMOS process. The long-term offset voltage drift has been calculated to be less than 0.5 muV over a period of 10 years at 55degC from a thermionic emission model for floating-gate charge loss. The offset voltage varies by a maximum of 130 muV over a temperature range of 170degC, thereby making this a viable approach to offset cancellation     

Successive Interference Cancellation Using Constellation Structure

An approach to successive interference cancellation is presented that exploits the structure of the combined signal constellation in a multiuser system. The asymptotic conditional efficiency of a successive detector is defined, based on the conditional probability of error at high signal-to-noise ratio (SNR), as a quantitative measure for evaluating detector performance at each stage of successive detection. The joint successive interference canceller (JSIC) that jointly detects consecutive users in an ordered set is proposed as an improvement over the conventional successive interference canceller (SIC). The maximal asymptotic conditional efficiency successive interference canceller (MACE-SIC) and its JSIC equivalent (MACE-JSIC) are also derived as the multiuser detectors that achieve the highest asymptotic conditional multiuser efficiency at each stage of successive detection among all possible SIC and JSIC detectors, respectively, given any particular ordering of user signals. The ordering of users achieving the highest asymptotic conditional efficiency at each stage of successive detection is derived. Performance bounds based on the signal constellation structure are derived to quantify the gain of the MACE-JSIC detector compared to the MACE-SIC detector.     

Inter-Relay Interference Cancellation Using MIMO Detection

Recent mobile applications have required high data rate. In metropolitan areas where data traffic is higher than other areas, heterogeneous networks (HetNet) are used to meet the traffic demand (Hoadley and Maveddat in IEEE Commun Mag 19(2):4–5, 2012). The HetNet has several low power base stations or remote radio heads in a macro cell coverage and sometimes coordinates the low power transmission points forming virtual multiple-input and multiple-output system. In this paper, inter-relay interference (IRI) cancellation for two-path relay system is considered. In existing schemes, IRI cancellation is performed at a destination node but proposed method performs the cancellation at relay nodes to reduce the complexity of detection algorithm for the destination node. Simulation results also show that the method of this paper achieves better BER performance than the existing schemes.     

Robust Multiuser Interference Cancellation for OFDM Systems With Frequency Offset

In orthogonal frequency division multiple access systems clusters of subcarriers are assigned to different users for parallel data transmissions. The subcarriers are overlapped, but orthogonal to each other such that there is no intercarrier interference (ICI). However, synchronization errors among users cause the loss of the orthogonality and introduce ICI resulting in multiple-access interference. Synchronization between users is particularly difficult in the uplink channel where the user signals are potentially asynchronous and affected by different frequency offsets due to misalignment in carrier frequencies and Doppler shifts. This paper proposes a method to lower the effects of different frequency offsets among user signals in an OFDMA uplink system. The multiple access interference due to the user frequency misalignments is reduced by reconstructing and removing the interfering signals in the frequency domain. An approach based on the selective cancellation method, is proposed and its performance is analyzed by means of theoretical analysis and computer simulations. The effectiveness of the proposed system has been evaluated in the case of ideal and no-ideal frequency offset estimation and has been compared with that of the classical successive and parallel cancellation schemes. Simulation results show that the proposed approach allows performance close to the ideal case, i.e., with ideal frequency synchronization among users, with a low increase of the implementation complexity. Moreover, it is also highlighted here, that the successive cancellation method slightly outperforms the selective scheme, at the expense of a higher computational complexity and processing delay     

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current–voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-$muhbox{m}$ CMOS process, the transconductor occupies 220 $,times,$160 $muhbox{m}^{2}$ active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.      

A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation

Current analog harmonic rejection mixers typically provide 30–40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30–45 dB.