High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

3100 V, asymmetrical, gate turn-off (GTO) thyristors in 4H-SiC

A 2-mm×2-mm, 4H-SiC, asymmetrical npnp gate turn-off (GTO) thyristor with a blocking voltage of 3100 V and a forward current of 12 A is reported. This is the highest reported power handling capability of 37 kW for a single device in SiC. The 5-epilayer structure utilized a blocking layer that was 50 μm thick, p-type, doped at about 7-9×10¹⁴ cm^-3. The devices were terminated with a single zone junction termination extension (JTE) region formed by ion-implantation of nitrogen at 650°C. The device was able to reliably turn-on and turn-off 20 A (500 A/cm²) of anode current with a turn-on gain (I_K/I_{G, on}) of 20 and a turn-off gain (I_K/I_{G, off}) of 3.3     

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm²) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/μs in these devices     

Inductive switching of 4H-SiC gate turn-off thyristors

The high-temperature operation of a silicon carbide gate turn-off thyristor is evaluated for use in inductively loaded switching circuits. Compared to purely resistive load elements, inductive loads subject the switching device to higher internal power dissipation. The ability of silicon carbide components to operate at elevated temperatures and high power dissipations are important factors for their use in future power conversion/control systems. In this work, a maximum current density of 540 A/cm² at 600 V was switched at a frequency of 2 kHz and at several case temperatures up to 150°C. The turn-off and turn-on characteristics of the thyristor are discussed     

Simulated turn-off of 4H-SiC gate turn-off thyristors with gateelectrodes on the p-base or the n-base

Turn-off simulations of a 4H-SiC GTO thyristor structure having a gated p-base and p-type substrate are compared with that having a gated n-base and n-type substrate. Two gate drive circuits are considered, one with a voltage source and resistor between the gate and adjacent emitter region, and the other with a voltage source and resistor between the gate and farthest emitter region. The gated n-base thyristor's substrate current increases atypically before the device turns off. Also, the gated n-base structure turns off when the gate circuit is connected directly to the emitter region furthest from the gate region, but the gated p-base structure does not. Furthermore, turn-off gain is lower for the gated n-base structure due to mobility differences as demonstrated by current-voltage (I-V) and current versus time (I-t) curves     

Ultrahigh-voltage high-current gate turn-off thyristors

High-power GTO's with ratings of 2500 V . 2000 A have been developed, and a 4500 V . 2000 A GTO was trial fabricated and performance tested, for use in traction motor control equipment. Their low ON-state voltage was attained by applying a unique anode emitter shorting structure which does not require doping of a lifetime killer such as gold to obtain suitable GTO characteristics. Their high interrupt current was obtained by introducing a ring-shaped gate structure which has uniform operation between many segments in the devices during turn-off process.     

2500-V 600-a gate turn-off thyristor (GTO)

GTO self-turn-off capability provides an advantage over an ordinary thyistor, because of forced commutation circuit removal upon inverter and chopper application, thus substantially reducing equipment size, weight, and mechanical noise. A series of high-power GTO's has been developed, with the present 2500-V-600-A unit as its peak. The most essential design problem for this unit is to establish a principle for increasing maximum gate turn-off current (IATO), while keeping overall thyristor characteristics in reasonable balance. High IATOwas attained by decreasing p-base sheet resistance, as well as decreasing n-emitter finger width. Excellent thyristor characteristics were obtained by adopting a low acceptor concentration near the cathode-gate junction. From a device process point of view, introducing a phosphorus redeposition annealing increased carrier lifetime in the p base to a sufficiently high level. This process contributed most strikingly to improving the off-state voltage.     

Turn-on process in 4H-SiC thyristors

Detailed turn-on measurements of 4H-Silicon Carbide (SiC) npnp thyristors are presented for a wide range of operating conditions. Comparisons with similarly-rated silicon and Gallium Arsenide thyristors show a superior rise time and pulsed turn-on performance of SiC thyristors. Rise time for a 400 V blocking voltage, 4 V forward drop (2.8×10³ A/cm²) SiC thyristor has been found to be of the order of 3-5 ns. Pulsed turn on measurements show a residual voltage of only 50 V when a current density of 10⁵ A/cm² (35 A) was achieved in 20 ns     

8000-V 1000-A gate turn-off thyristor with low on-state voltage andlow switching loss

An 8 kV, 1 kA gate turn-off thyristor (GTO) that has been designed with a combination of a p-i-n structure and a ringed-anode short structure is discussed. The GTO has been fabricated using a diffusion and epitaxial buffer process. As a consequence, low on-state voltage and low switching loss have been achieved, solving the two major problems in high-voltage GTOs. The device's structure, the p-i-n base process, and the electrical characteristics of the GTO are described     

Efficiency of gate control in double-interdigitated (TIL) GTO thyristors

The research reported in this work was focused on the efficiency of gate control during turn-off in the recently developed double-interdigitated (TIL) GTO thyristors. The 8 mm² area, TO-220 packaged, high voltage test devices were investigated under both current and voltage input conditions. The main monitored parameters were: the peak turn-off gain K_off(max), the components of the turn-off time and the gate pulse width t_gr. During the tests the TIL GTOs were driven up to an anode current i_T = 50 A, a value equal to the non-repetitive peak on-state current (I_TSM) of these thyristors.The performed investigations have shown that these novel GTO devices possess a good efficiency of gate control expressed by: 1) low power consumption by the gate under both current and voltage drive conditions; 2) extremely high turn-off gain K_off(max), which is an increasing function of the anode current in a wide range of gate signals amplitudes and durations; 3) fast turn-off of large amounts of anode current with relatively short gate pulse widths; 4) substantial reduction of the storage time t_s and fall time t_f through adequate current or voltage drive. Design/behavioral details are given, which are useful in the implementation of the TIL concept in GTOs and other power switching devices, such as the bipolar transistors.     

4.5-kV injection-enhanced gate transistors (IEGTs) with high turn-off ruggedness

Although high blocking voltage insulated gate bipolar transistors (IGBTs) have wider safe operating areas (SOAs) than do gate turn-off thyristors, a failure problem remains at turn-off transient. The purpose of this paper is to clarify the mechanism of failure at turn-off transient and to develop a high-voltage injection-enhanced gate transistors (IEGTs) with wide SOA at turn-off transient [wide reverse-biased SOA (RBSOA)]. We discuss this destruction mechanism in detail on the basis of comparison of experimental results with calculated results obtained by an analytical model considering dynamic avalanche generation. These results lead to the conclusion that the design of the n-emitter and the control of avalanche generation onset are key parameters for realizing high ruggedness of high-voltage IEGT. Based on the proper design of the n-emitter and the gate driving condition, a high-voltage and high-current 4.5-kV IEGT with wide RBSOA, keeping low saturation voltage and low turn-off switching loss, has been successfully developed.     

Theoretical and Experimental Analyses of Safe Operating Area (SOA) of 1200-V 4H-SiC BJT

The safe operating area (SOA) of 1200-V SiC bipolar junction transistor (BJT) is investigated by experiments and simulations. The SiC BJT is free of the second breakdown even under the turn-off power density of 3.7 $hbox{MW/cm}^{2}$. The theoretical boundary of reverse-biased SOA caused by the false turn-on is obtained by simulations. The short-circuit capability of the 1200-V SiC BJT is also investigated theoretically and experimentally. Self-heating is considered by the nonisothermal simulation, and $sim$1800-K maximum local temperature is the simulated critical temperature of device failure. The surface condition is very critical for short-circuit capability. From simulations, when the interface trap density increases, the critical temperature decreases. This is believed to be the reason why the experimental results show much shorter short-circuit withstand time than the simulation showed.      

Geometrical effects in high current gain 1100-V 4H-SiC BJTs

This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain /spl beta/=64 and a breakdown voltage of 1100 V. The high /spl beta/ value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on /spl beta/. A minimum distance of 2-3 /spl mu/m between the emitter edge and base contact implant was found adequate to avoid a substantial /spl beta/ reduction.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

430-V 12.4-$hboxmOmegacdot hboxcm^2$Normally off 4H-SiC Lateral JFET

This letter reports the experimental demonstration of the first 4H-SiC normally off high-voltage lateral junction field-effect transistor. The design and fabrication of such a device have been investigated. The fabricated device has a vertical channel length of 1.8$muhboxm$created by tilted aluminum implantation on the sidewalls of deep trenches and a lateral drift-region length of 5$muhboxm$. Normally off operation$(V_ GS=hbox0 V)$with a blocking voltage$V_ br$of 430 V has been achieved with a specific on-resistance$R_ onhbox- sp$of 12.4$hboxmOmega cdot hboxcm^2$, which is the lowest specific on-resistance for 4H-SiC lateral power switches reported to date, resulting in a$V_ br^2/R_ onhbox- sp$value of 15$hboxMW/cm^2$. This is among the best$V_ br^2/R_ onhbox- sp$figure-of-merit reported to date for 4H-SiC lateral high-voltage devices.     

Turn-off operation of a MOS-gate 2.6 kV 4H–SiC gate turn-off thyristor

The turn-off operation of a 4H–SiC gate turn-off thyristor (GTO) with 2.6 kV breakover voltage has been investigated using an external Si-MOSFET as a gate-to-emitter shunt (MOS-gate mode), in the temperature interval 293–496 K. The maximum cathode current density j_cmax that can be turned off in such a mode decreases from 1850 A/cm² at 400 K to 700 A/cm² at 496 K. The room temperature j_cmax value is estimated to be about 3700 A/cm². The above j_cmax values are essentially higher than those observed when turning this thyristor off in the conventional GTO mode. Turn-off transients in the MOS-gate mode have been studied in both quasi-static and pulse regimes. Temperature dependencies of the turn-on and turn-off times, as well as those of the turn-on and turn-off energy losses have been measured. The upper switching frequency of the GTO is estimated to be about 700 kHz.     

Trench-gate base-resistance-controlled thyristors (UMOS-BRTs)

Two base-resistance-controlled thyristor (BRT) structures with trench (UMOS) gate regions are described. A model for the maximum controllable current density for these devices is proposed and demonstrated to agree well with experimental results obtained on devices with 600-V forward-blocking capability     

High-voltage (3 kV) UMOSFETs in 4H-SiC

Vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) in 4H-SiC having both trench oxide protection and junction termination extension (JTE) are reported for the first time. Devices are fabricated with and without counter-doped channels. Blocking voltages and specific on-resistances are 3360 V and 199 mΩ-cm² for doped-channel FETs and 3055 V and 121 mΩ-cm² for FETs without doped channels. These blocking voltages are the highest reported to date for UMOSFETs in SiC     

Effects of rapid thermal annealing on nitrided gate oxide grown on 4H-SiC

The electrical characteristics of thermally nitrided gate oxides on n-type 4H-SiC, with and without rapid thermal annealing processes, have been investigated and compared in this paper. The effects of annealing time (isothermal annealing) and annealing temperature (isochronal annealing) on the gate oxide quality have also been systematically investigated. After rapid isothermal and isochronal annealings, there has been a significant increase in positive oxide-charge density and in oxide-breakdown time. A correlation between the density of the positive oxide charge and the oxide breakdown reliability has been established. We proposed that the improvement in the oxide-breakdown reliability, tested at electric field of 11 MV/cm, is attributed to trapping of injected electron by the positive oxide charge and not solely due to reduction of SiC-SiO₂ interface-trap density.     

Conduction mechanisms in thermal nitride and dry gate oxides grown on 4H-SiC

The charge conduction mechanisms in Metal-Oxide-Semiconductor (MOS) capacitors formed on n-type 4H-silicon carbide (SiC) using thermally grown silicon dioxide (SiO₂) as gate dielectrics are analyzed. The possible conduction mechanisms have been identified in the whole measurement range. At high electric fields, the charge conduction is dominated by Fowler–Nordheim tunneling. In addition, trap assisted tunneling and ohmic type conduction are considered to explain the cause of leakages detected at intermediate and low oxide electric fields. Various electronic parameters are extracted. The oxide breakdown strengths are higher than 8 MV/cm. Fowler–Nordheim tunneling barrier height was found to be 2.74 eV for nitride oxides and 2.54 eV for dry oxides at high electric field regions and the trap energy level extracted using trap assisted tunneling emission model was estimated to be about 0.3 eV for both oxides. The possible contribution of the Poole–Frenkel effect to the conduction mechanism was also considered, and it was found that it does not play a dominant role.