High-Performance and Low-Temperature-Compatible p-Channel Polycrystalline-Silicon TFTs Using Hafnium-Silicate Gate Dielectric

In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium- silicate (HfSiO_x) gate dielectric are demonstrated with low- temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiO_x gate dielectric exhibit excellent device performance in terms of higher I_ON/I_OFF current ratio, lower subthreshold swing, and lower threshold voltage (V_th) albeit with slightly higher OFF-state current. More importantly, the mobility of TFTs with HfSiO_x gate dielectric is 1.7 times that of TFTs with conventional deposited-SiO₂ gate dielectric.     

Comparison of deep-submicrometer conventional and retrograden-MOSFETs

An extensive comparison of the deep-submicrometer conventional and retrograde n-MOSFETs designed for either a low-power or a high-performance technology is made. We compare simulated curves of off-current versus channel length (I_OFF-L) and on-current vs. channel length (I_ON-L). We include parametric dependence upon the channel length L, and aspects of the doping profile, namely surface doping N_S, bulk doping N_B, and depth of the lightly doped surface layer d. At a given L, the comparison of structures with the same I_ON shows that all retrograde profiles exhibit much worse I_OFF. On the other hand, comparison of structures with the same I_OFF shows that all retrograde profiles have lower I_ON. Moreover, judging the short-channel advantages of a proposed device structure based upon the V _T-L roll-off curve without examination of the related I_OFF-L and I_ON-L curves could lead to a mistaken technology assessment     

Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using $hbox{Pr}_{2}hbox{O}_{3}$ Gate Dielectric

In this paper, we have developed high-k Pr₂O₃ poly-Si thin-film transistors (TFTs) using different N₂O plasma power treatments. High-k Pr₂O₃ poly-Si TFT devices using a 200-W plasma power exhibited better electrical characteristics in terms of high effective carrier mobility, high driving current, small subthreshold slope, and high I_ON/I_OFF current ratio. This result is attributed to the smooth Pr₂O₃/poly-Si interface and low interface trap density. Pr₂O₃ poly-Si TFT with a 200-W N₂O plasma power also enhanced electrical reliabilities such as hot carrier and positive bias temperature instability. All of these results suggest that a high-k Pr₂O₃ gate dielectric with the oxynitride buffer layer is a good candidate for high-performance low-temperature poly-Si TFTs.     

Source-field-plated Ga2O3 MOSFET with a breakdown voltage of 550 V

Ga_2O_3 metal–oxide–semiconductor field-effect transistors(MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga_2O_3 film, which was grown by metal organic chemical vapor deposition(MOCVD) on an Fedoped semi-insulating(010) Ga_2O_3 substrate. The structure consisted of a 400 nm unintentionally doped(UID) Ga_2O_3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO_2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_gs of 3 V. The off-state current was as low as 7.1 ×10^-11 A/mm, and the drain current I_ON/I_OFF ratio reached 10~9. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.     

Improving Switching Performance of Thin-Film Transistors in Disordered Silicon

The silicon integrated electronics on glass or plastic substrates attracts wide interests. The design, however, depends critically on the switching performance of transistors, which is limited by the quality of silicon films due to the materials and substrate process constraints. Here, the ultrathin channel device structure is proposed to address this problem. In a previous work, the ultrathin channel transistor was demonstrated as an excellent candidate for ultralow power memory design. In this letter, theoretical analysis shows that, for an ultrathin channel transistor, as the channel becomes thinner, stronger quantum confinement can induce a marked reduction of OFF-state leakage current (I_OFF), and the subthreshold swing (S) is also decreased due to stronger control of channel from the gate. Experimental results based on the fabricated nanocrystalline silicon thin-film transistors prove the theoretical analysis. For the 2.0-nm-thick channel devices, I_ON/I_OFF ratio of more than 10¹¹ can be achieved, which can never be obtained for normal thick channel transistors in disordered silicon.     

Logic Suitability of 50-nm In0.7 Ga0.3As HEMTs for Beyond-CMOS Applications

We have experimentally studied the suitability of nanometer-scale In_0.7Ga_0.3As high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm gate-length In_0.7Ga_0.3As HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height (Phi_B) and insulator thickness (t_ins) on the logic characteristics of In_0.7Ga_0.3As HEMTs. The best 50-nm HEMTs with the highest Phi_B and the smallest t_ins exhibit an I_ON/I_OFF ratio in excess of 10⁴ and a subthreshold slope (S) below 86 mV/dec. These nonoptimized 50-nm In_0.7Ga_0.3As HEMTs also show a logic gate delay (CV/I) of around 1 ps at a supply voltage of 0.5 V, while maintaining an I_ON/I_OFF ratio above 10⁴, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.     

Lateral and Vertical Scaling of $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In_0.7Ga_0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In_0.52Al_0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature V_T = -0.02 V, DIBL = 93 mV/V, S = 88 mV/V, and I_ON/I_OFF = 1.6 times10⁴, at V _DD = 0.5 V. We also estimate a gate delay of CV/I = 1.6 ps at V_DD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit 1.2times more current drive (I_ON) than the state-of-the-art 65-nm low-power CMOS technology at V _DD = 0.5 V.     

Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of In0.52Al0.48As/In0.53Ga0.47As p-HEMTs

The characteristics of 0.15- mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In_0.52AI_0.48As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In_0.52Al_0.48As barrier. The 0.15-mum InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G_m,max (1.38 S/mm), I_ONn/I_OFF(1.18X10⁴), drain-induced barrier lowering (80 mWV), threshold voltage uniformity (V_th,avg = -190 mV and alpha = 15 mV), and ftau (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.     

Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits

Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-V_t circuits, but are plagued by increased variation and reduced I_ON/I_OFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Improved High-Temperature Leakage in High-Density MIM Capacitors by Using a TiLaO Dielectric and an Ir Electrode

We have fabricated high-kappa TaN/Ir/TiLaO/TaN metal-insulator-metal capacitors. A low leakage current of 6.6 times 10^-7 A/cm² was obtained at 125degC for 24-fF/mum2 density capacitors. The excellent device performance is due to the combined effects of the high-kappa TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.     

Thickness Scaling and Reliability Comparison for the Inter-Poly High- κ Dielectrics

In this letter, the inter-poly dielectric (IPD) thickness, scaling, and reliability characteristics of Al₂O₃ and HfO₂ IPDs are studied, which are then compared with conventional oxide/nitride/oxide (ONO) IPD. Regardless of deposition tools, drastic leakage current reduction and reliability improvement have been demonstrated by replacing ONO IPD with high-permittivity (high-kappa) IPDs, which is suitable for mass production applications in the future. Moreover, metal-organic chemical vapor deposition (MOCVD) can be used to further promote dielectric reliability when compared to reactive-sputtering deposition. By using the MOCVD, the charge-to-breakdown (Q_BD) can be significantly improved, in addition to enhanced breakdown voltage and effective breakdown field. Our results clearly demonstrate that high- IPD, particularly deposited by MOCVD, possesses great potential for next-generation stacked-gate Flash memories.     

Analysis of Strain Effects in Ballistic Carbon Nanotube FETs

The effect of uniaxial and torsional strain on the performance of ballistic carbon nanotube (CNT) Schottky-barrier (SB) field-effect transistors (FETs) is examined by self-consistently solving the Poisson equation and the Schroumldinger equation using the nonequilibrium Green's function formalism. A mode space approach can be used to reduce the computational cost of atomistic simulations for the strained CNTs by orders of magnitude. It is shown that even a small amount of uniaxial (< 2%) or torsional (<5deg) strain can result in a large effect on the performance of the CNTFETs due to the variation of the band gap and band-structure-limited velocity. Semiconducting CNT channels with different chiralities are influenced in drastically different ways by a certain applied strain, which is determined by a (n-m) mod 3 rule. In general, a type of strain which produces a larger band gap results in increased SB height and decreased band-structure-limited velocity, and hence a smaller minimum leakage current, smaller on current, larger maximum achievable I_ON/I_OFF, and larger intrinsic delay. The other type of strain that reduces the band gap results in the opposite effect on the device performance metrics of the CNTFETs     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (L_gges0.35 mum), exhibit excellent device performance with high I_ON/I_OFF ratio (~10⁶), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $kappa$ LTPS-TFT

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO₂ low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I_min is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO₂ gate dielectric and fluorine preimplantation can simultaneously achieve low V_TH ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high I_ON/I_min current ratio ~1.98 times 10⁷.     

Stress Engineering in High-$kappa$ FETs for Mobility and On-Current Enhancements

We present a systematic study of uniaxial/biaxial stress effects on low-field mobility and on-current in high-kappa n/pFETs. It is found that mobility enhancement by strain in high-kappa FETs is smaller than SiO₂ FETs in low effective field because of remote Coulomb scattering caused by fixed charges inside high-kappa films, while mobility enhancement by biaxial tensile strain in high-kappa nFETs is greater than SiO₂ nFETs in high effective field due to weaker surface roughness scattering in high-kappa nFETs. In short-channel high-kappa nFETs, better on-current improvement by biaxial tensile strain than in SiO₂ nFETs is achieved as a result of both higher mobility enhancement and weaker velocity saturation. The optimum stress design for high-kappa n/pFETs is also discussed, and it is concluded that the application of transverse tensile stress, in addition to conventional longitudinal stress, is essential for performance improvement of high-kappa n/pFETs.     

Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV-Ozone Oxide

In this letter, the electrical properties of a HfAlON dielectric with UV-O₃ interfacial oxide were comprehensively studied and then compared with those of a HfAlON dielectric with interfacial chemical oxide. In the comparison of dielectric characteristics including leakage current density, transconductance, subthreshold swing, saturation drain current, effective electron mobility, and constant voltage stress reliabilities, the results clearly indicate that high-density interfacial UV-O₃ oxide is beneficial in reducing both bulk and interface traps as well as diminishing stress-induced trap generation, and possesses a high potential to be integrated with further high-kappa dielectric applications.