Ionising radiation effects on MOSFET drain current

We have investigated the radiation effect on MOSFET performances due to the incidence of a few ions in the gate area. We present new experimental evidence that a single ion may lead to the MOSFET drain current collapse, due to the formation of a localized oxide damaged region over a large portion of the channel width, well before the breakdown onset. We call these phenomena single event drain current collapse (SEDC²). This effect is evident in devices with small channel width (W), i.e., comparable to the size of damaged region, and fades as W increases over the size of the ion damaged region.     

Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact

This letter reports the first full process integration of nanocrystal memory cell with 4.6 F/sup 2/ area ( NOR type), which is achieved by direct tungsten (W) bitline on self-aligned landing plug polysilicon contact. Prior to the nanocrystals (NCs) formation, surface hydroxylation of the tunnel SiO/sub 2/ by exposure to 1:99 hydrogen flouride (HF) is performed to maintain controllability of NCs. Also, the degradation of the tunnel SiO/sub 2/ caused by HF dipping is overcome to some extent through its fluorination. Robust four-threshold voltage (V/sub th/) states for 2-bit operation per cell are observed due to the localized injected charge and V/sub th/ asymmetry from different reading sensitivity to localized charges.     

A 3-D sidewall flash EPROM cell and memory array

A new 3-D sidewall flash EPROM cell has been implemented in a novel memory array. The sidewall cell is a single-transistor stacked gate cell built on the sidewalls of a silicon pillar. The gates surround the pillar and current flows vertically from top to bottom of the pillar. The cell size approaches the square of the minimum pitch and is less than 40% of that of the conventional NOR-type structure. The cell and array architecture promise to be highly scalable     

Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance

The write/erase characteristics of Germanium nanocrystal memory device are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. A trap model is proposed to describe the retention characteristic of the nanocrystal memory. The impact of nanocrystal size, tunnel-oxide thickness, and high-k tunnel material is studied, and the suitability of the nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed. Issues related to the scaling limit of the nanocrystal memory device are investigated.     

Performance of the 3-D PENCIL flash EPROM cell and memory array

A promising new 3-D Programmable Erasable Nonvolatile CylIndricaL (PENCIL) flash EPROM cell that offers significant area and performance advantages over conventional planar approaches has been implemented in a novel memory array. The 3-D PENCIL cell is a vertical device formed on the sidewalls of an etched silicon pillar. The cell is a single transistor stacked gate structure with the floating gate and control gate completely surrounding the pillar. Current flows vertically from the bit line contact at the top of the pillar to the source lying at the bottom of the pillar. When implemented in a novel self-aligned array, the cell size approaches the square of the minimum pitch and has an area less than half that of the conventional NOR type structure. The cell and array architecture also promise to be highly scalable. Experimental data reveals that the cells have up to 3× larger read current than comparable planar cells, are suitable for 5 V only operation and have fast program and erase speeds at moderate voltage levels. Uniformity and endurance characteristics are also promising     

Image processing on a memory array architecture

In this paper we examine the usefulness of a simple memory array architecture to several image processing tasks. This architecture, called theAccess Constrained Memory Array Architecture (ACMAA) has a linear array of processors which concurrently access distinct rows or columns of an array of memory modules. We have developed several parallel image processing algorithms for this architecture. All the algorithms presented in this paper achieve a linear speed-up over the corresponding fast sequential algorithms. This was made possible by exploiting the efficient local as well as global communication capabilities of the ACMAA.     

Test results on an MNOS memory array

The NCR 2050 MNOS memory chip, developed under Air Force contract for frequency-preset applications in communications equipment, has been tested and evaluated. Results on retentivity, writing characteristics, pattern sensitivity, and endurance are presented.     

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100 kHz–2.0 MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.     

碳纳米管阵列辐射的实验研究

为了对碳纳米管阵列的辐射特性进行实验研究,通过采用在微带天线上加载碳纳米管阵列的方法对碳纳米管阵列进行馈电,并比较了两种微带天线加载碳纳米管阵列辐射方向图的变化,结果发现加载前后天线的S11以及辐射方向图均有明显变化,说明碳纳米管阵列能够显著改变天线的辐射特性,与理论预测相符。最后针对实验现象做了一些定性的解释。     

Phase change memory alloys: GST cell array characterization using picosecond ultrasonics

Phase change random access memory alloys (PRAM or PCM) are a class of non-volatile memory that is thought as viable alternatives to flash memory technology or to supplement other memory technologies depending on the end applications and its key performance requirements. Ge₂Sb₂Te₅ alloy (GST) is the most widely used chalcogenide material for PCM application, and has many unique properties, including strong temperature-dependent film properties, low thermal conductivity, and high electrical resistivity. Picosecond ultrasonics was used to make non-contact, non-destructive measurements of GST films on blanket wafers and directly on product wafers. On-product wafer measurements were made on various via array (0.5 μm and 1 μm between cell edges with CD size from 250 to 800 nm). Measurements have shown excellent correlation to cross-section SEM and were consistent with CMP polish times for both blanket and pattern wafer measurement. Excellent repeatability based on extensive measurements demonstrates the capability and reliability of picosecond ultrasonic technology. Picosecond ultrasonic measurements also provide rapid characterization across the whole wafer at production-worthy throughputs.     

宽谱光源对CMOS阵列电串扰的影响

CMOS阵列探测器中,像素单元间的串扰会影响其成像质量。为了解不同光源对CMOS电串扰的影响,针对CMOS图像传感器的电串扰特性建立了一个分析模型,结合CMOS图像传感器的工作原理定量计算了单色光、宽谱光源入射条件下的电串扰特性。分析结果表明CMOS图像传感器的电串扰随单色光波长、宽谱光源谱宽和中心波长的增大而增大,但中心波长与单色光波长相同的宽谱光源,其对电串扰的影响大于单色光。辐照功率为600 W,单色光波长为1 064 nm,电串扰大小约为50.611 mV;宽谱光源中心波长为1 064 nm,谱宽为400 nm时,电串扰的大小约为50.914 mV,相比于单色光电串扰增加了约0.303 mV。     

基于DMA的高速数据闪存阵列的设计

针对测控系统中海量数据的快速存储,设计了一种基于DMA的数据存储阵列系统。它是以FPGA为平台构建的SOPC系统,内含软核处理器Microblaze和包含DMA控制器的用户自定义IP,其中DMA控制器实现了对闪存阵列的编程命令、地址的传输,以及存储阵列的流水线编程,提高了传统的由CPLD与单片机组成的存储测试系统的速度。     

Microelectrode array fabrication by electrical discharge machining and chemical etching

Wire electrical discharge machining (EDM), with a complementary chemical etching process, is explored and assessed as a method for developing microelectrode array assemblies for intracortically recording brain activity. Assembly processes based on these methods are highlighted, and results showing neural activity successfully recorded from the brain of a mouse using an EDM-based device are presented. Several structures relevant to the fabrication of microelectrode arrays are also offered in order to demonstrate the capabilities of EDM.     

Large-bandwidth flat cylindrical array with circular polarisation and omnidirectional radiation

Experimental properties of a flat cylindrical array with circular polarisation and omnidirectional radiation are presented. The thickness of the array wrapped on a perfect conducting cylinder is 0.04?0. A bandwidth of 10% has been obtained. It is now possible to decrease the thickness by a factor 2 (i.e. to 0.02?0), when using a short-circuited elementary source instead of a flat folded dipole, and yet retain the same band-width.     

Storage array and sense/refresh circuit for single-transistor memory cells

For the cell layout in silicon-gate technology a storage capacitor is proposed that uses a field-induced nonequilibrium inversion layer as an electrode. As a sensitive refresh amplifier a gated flip-flop that can be used for one digit line at each of its two input nodes is presented. Different cells and refresh circuits have been realized in silicon-gate technologies. Cells with an area of 1600 /spl mu/m/SUP 2/(2.6 mil/SUP 2/) have been successfully operated with a READ/WRITE cycle time of 350 ns (storage capacitance 0.134 pF, digit line capacitance 0.32 pF for 64 cells per line or 128 cells per amplifier).     

Effect of stress on the electrical resistivity of solder

The electrical resistivity of tin-lead eutectic solder was found to increase upon tension. The effect was partially reversible. The fractional change in resistance per unit strain was 60. The irreversible part of the effect was due to plastic deformation.     

基于频率分集阵列的聚束SAR虚拟辐射源

频率分集阵列作为一种新型阵列天线模型,无需移相器就可在空间实现波束扫描。基于频率分集均匀线阵模型,研究了聚束合成孔径雷达系统发射信号传输特性,引出了虚拟辐射源的概念,对其位置进行分析,与实际辐射源位置进行比较,可有效提高成像方位向分辨力,对于提高雷达隐身性能和进行电子欺骗也具有重要意义。计算机仿真实验验证了理论推导的准确性。     

The influence of parameter dispersion of electrical cells on the array power output

Energy conversion by electrical (photovoltaic and chemical) cells are of relatively low power and low voltage levels. The cells are therefore connected in an array to produce the higher power and voltage levels desired. The dispersion of the cell parameters affect the array performance in such a way that the power output is lower than that desired, and hence additional cells have to be added. A larger dispersion of the parameters requires a greater amount of additional cells for the same power output requirement to make up for the so-called cell mismatch losses. This paper deals with the influence of parameter dispersions on array output power. The required number of cells in an array is determined analytically for a known distribution of the cell parameters. The nonidentical cell array can now be interchanged with an equivalent identical cell array permitting less complex calculations. The analysis in this paper is given for a large number of ideal electrochemical cells; a similar approach can be applied on other electrical cells.     

Transient and total dose radiation characteristics of an SOS LSI array

Transient and total dose characteristics of irradiated 300 gate LSI arrays are presented. These arrays are configured to carry out the arithmetic function of an Arithmetic-Logic Unit. Samples were fabricated with ion implanted source-drain regions, wet-or dry-oxide (SiO2) gate insulator, and n⁺deposited polysilicon gates. Irradiation sources were the AFCRL Linac operating with 20- and 100-ns pulses, and the Fort Monmouth Cobalt 60 facility. Transient upset measurements of four worst case outputs are presented with the samples operating in an active and static mode during exposure. Worst case is the static mode of operation during exposure. The upset dose rate during an active mode depends on the time of occurrence of the radiation pulse relative to the transition waveform. Functional failure doses made in-situ are presented for exposure dose rates ranging from 4.2 to 1000 krads (Si)/h. Corresponding total dose failure for these dose rates varies from 10⁵to 10⁶rads (Si). The rapid annealing properties of the gate insulator are responsible for this dependence on dose rate.