Investigation on the Electric Properties of $ hbox{Bi}_{1.5}hbox{ZnNb}_{1.5}hbox{O}_{7}$ Thin Films Grown on TiN Substrate for MIM Capacitors

A small crystalline phase was formed in the Bi_1.5ZnNb_1.5O₇ (BZN) film grown at 300degC on TiN/SiO₂/Si substrate using RF-magnetron sputtering. A 46-nm-thick BZN film exhibited a high capacitance density of 13.6 fF/mum² at 100 kHz with a dielectric constant of 71, which did not change even in the gigahertz range (1-6 GHz). The quality factor was high, approximately 50, at 2.5 GHz. The leakage-current density was low, approximately 5.66 nA/cm², at 2 V. The quadratic voltage and temperature coefficients of capacitance were approximately 631 ppm/V² and 149 ppm/degC at 100 kHz, respectively. These results indicate that the BZN film grown on TiN substrate at 300degC can be a good candidate material for metal-insulator- metal capacitors.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

RF and Logic Performance Improvement of $ hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}/hbox{InAs}/hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high g_m value of 1590 mS/mm at V_d = 0.5 V, the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f_T achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.     

Comparison of MONOS Memory Device Integrity When Using $hbox{Hf}_{1 - x - y}hbox{N}_{x}hbox{O}_{y}$ Trapping Layers With Different N Compositions

We have studied the nitrogen composition dependence of the characteristics of Hf_1-x-yN_xO_y/SiO₂/Si MONOS memory devices. By increasing the N composition in the Hf_1-x-yN_xO_y trapping layer, both the memory window and high-temperature retention improved. The Hf_0.3N_0.2O_0.5 MONOS device displayed good characteristics in terms of its plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85degC or 1.5 V at 125degC.     

10-Gb/s, 80-km SMF Transmission From 0 to 80 $^{circ}$C by Using L-Band InGaAlAs-MQW Electroabsorption Modulated Laser With Twin Waveguide Structure

A 10-Gbit/s, 1.58-mu m, InGaAlAs electroabsorption modulator (EAM) integrated distributed-feedback (DFB) laser (EML) with a twin waveguide (TWG) structure is operated experimentally over a wide temperature range of 0 to 80degC. We introduce an InGaAlAs multi-quantum well (MQW) system for both LD and EAM MQWs, because this material has temperature-tolerant characteristics. These layers are grown using single step epitaxial growth, and the device was fabricated with a very simple process. Moreover, successful transmission through an 80-km single-mode fiber (SMF) was achieved with the device running at up to 80degC. These results confirm the suitability of this type of laser for use as a cost-effective and low-power consumption light source in 10-Gbit/s optical network systems.     

Sub-$hbox{100-}muhbox{A}$ Reset Current of Nickel Oxide Resistive Memory Through Control of Filamentary Conductance by Current Limit of MOSFET

Resistive random access memory consisting of NiO resistive memories and control transistors was fabricated with 0.18-mum CMOS technology. An initial forming voltage as low as 2 V was achieved with thin NiO film, and a reset current lower than 100 muA was realized by using the current limit of a selected cell transistor in the set process (1T-1R). The current level was determined by its gate voltage, resulting in the control of electrical resistance of the filamentary conductive paths in the low resistive state. Furthermore, a large voltage increase in the reset operation, which may cause an undesirable set operation, was also suppressed by a voltage-clamp transistor connected to the 1T-1R cell in series. On the basis of these proposed switching schemes, the stable pulse operation was demonstrated successfully. In addition, both nonvolatile data retention at 150degC and operation in a wide temperature range (from -40degC to 150degC) were confirmed.     

Excellent Switching Uniformity of Cu-Doped $hbox{MoO}_{x}/hbox{GdO}_{x}$ Bilayer for Nonvolatile Memory Applications

We have investigated a Cu-doped MoO_x/GdO_x bilayer film for nonvolatile memory applications. By adopting an ultrathin GdO_x layer, we obtained excellent device characteristics such as resistance ratio of three orders of magnitude, uniform distribution of set and reset voltages, switching endurance up to 10⁴ cycles, and ten years of data retention at 85degC. By adopting bilayer films of Cu-doped MoO_x/GdO_x, a local filament was formed by a two-step process. Improved memory characteristics can be explained by the formation of nanoscale local filament in the ultrathin GdO_x layer.     

Resistive Memory Switching of $hbox{Cu}_{x}hbox{O}$ Films for a Nonvolatile Memory Application

Poly crystalline Cu_xO films produced by plasma oxidation are investigated for nonvolatile memory applications. Reversible bistable resistive switching from a high-resistance state to a low-resistance state, and vice versa, is observed in an integrated Al/Cu_xO/Cu structure under voltage sweeping. More than 3000 repetitive cycles are observed in 180-mum memory devices with an on/off ratio of ten times. Data testing shows that the devices meet the ten-year retention requirement for the storage of programmed logic signals.     

Ge-on-SOI-Detector/Si-CMOS-Amplifier Receivers for High-Performance Optical-Communication Applications

In this paper, an overview and assessment of high-performance receivers based upon Ge-on-silicon-on-insulator (Ge-on-SOI) photodiodes and Si CMOS amplifier ICs is provided. Receivers utilizing Ge-on-SOI lateral p-i-n photodiodes paired with high-gain CMOS amplifiers are shown to operate at 15 Gb/s with a sensitivity of -7.4 dBm (BER=10^-12) while utilizing a single supply voltage of only 2.4 V. The 5-Gb/s sensitivity of similar receivers is constant up to 93 degC, and 10-Gb/s operation is demonstrated at 85 degC. Error-free (BER<10^-12) operation of receivers combining a Ge-on-SOI photodiode with a single-ended high-speed receiver front end is demonstrated at 19 Gb/s, using a supply voltage of 1.8 V. In addition, receivers utilizing Ge-on-SOI photodiodes integrated with a low-power CMOS IC are shown to operate at 10 Gb/s using a single 1.1-V supply while consuming only 11 mW of power. A perspective on the future technological capabilities and applications of Ge-detector/Si-CMOS receivers is also provided     

Pressure Contact Micro-Springs in Small Pitch Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. The springs are beams which curl out of the surface and can be used for wafer-scale testing and packaging. They are fabricated with standard wafer-scale thin film techniques and have been previously demonstrated on active silicon integrated circuits. Single springs and their electrical contacts are characterized with force versus compression and compression versus resistance measurements. Flip-chip packages with hundreds of micro-springs were assembled with 20-mum pad pitch and 40-mum spring pitch. Each spring operates with a force of approximately 0.01 g and contacts a gold pad. These packages are shown to have stable resistance values during both in-situ thermocycle (0degC to 125degC) and humidity testing (60degC at 95%RH). Spring electrical contacts inside the package are shown not to degrade during environmental testing through measurements of four-wire resistance and electrical isolation structures. High-speed glitch measurements are performed to confirm that the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Low-Voltage and High-Speed Operations of 30-nm-Gate Pseudomorphic $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}/hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$ HEMTs Under Cryogenic Conditions

In this letter, we fabricated 30-nm-gate pseudomorphic In_0.52 Al_0.48As/In_0.7Ga_0.3As HEMTs with multilayer cap structures to reduce source and drain parasitic resistances; we measured their dc and radio-frequency characteristics at 300, 77, and 16 K under various bias conditions. The maximum cutoff frequency fT was 498 GHz at 300 K and 577 GHz at 77 K. The maximum fT exceeded 600 GHz at 16 K. Even at a drain-source voltage V _ds of 0.4 V, we obtained an fT of 500 GHz at 16 K. This indicates that cryogenic HEMTs are favorable for low-voltage and high-speed operations. Furthermore, the present 30-nm-gate HEMTs at 300 K show almost the same fT values at the same dc-power dissipation as compared to 85-nm-gate InSb-channel HEMTs. The improvement of the maximum-oscillation-frequency f _max values was also observed at 77 and 16 K.     

Wide Temperature Range Operation of a 1.55-$mu$m 40-Gb/s Electroabsorption Modulator Integrated DFB Laser for Very Short-Reach Applications

We present the uncooled operation of a 1.55- mum 40-Gb/s InGaAlAs electroabsorption modulator (EAM) integrated distributed-feedback (DFB) laser within a temperature range of 95degC (-15degC to 80degC ). To the best of our knowledge, this is the largest temperature range reported so far for such a 40-Gb/s EAM integrated DFB laser. We designed the EAM to operate at high speed by reducing the electrical parasitics, and we achieved a 3-dB frequency bandwidth of over 39 GHz for an EAM length of less than 150 mum. We demonstrated a 2-km single-mode fiber (SMF) transmission at 40-Gb/s over a wide temperature range of -15degC to 80degC by adjusting only the bias voltage to the EAM while keeping the modulation voltage swing constant at 2.0 V when the temperature changed. We achieved a dynamic extinction ratio of over 8.2 dB and a 2-km SMF transmission with a power penalty of less than 2 dB over a wide temperature range.     

10-Gb/s Direct Modulation up to 100 $^{circ}$C Using 1.3- $mu$m-Range Metamorphically Grown Strain Compensated InGaAs–GaAs MQW Laser on GaAs Substrate

We have realized 10-Gb/s direct modulation up to 100degC using a metamorphic InGaAs multiple-qunatum well (MQW) laser on a GaAs substrate. The highly strained InGaAs quantum well (QW) and strain-compensated GaAs barrier layer allowed 1.3-mum-range lasing and an increased number of QWs (six). This laser with a 200-mum-long short cavity and a narrow ridge had maximum relaxation oscillation frequencies of 13 and 6 GHz at 25degC and 100degC, respectively. A 10-km single-mode fiber error-free transmission was successfully obtained at a temperature of 85degC .     

Dual-Color Electroluminescence ($lambda approx hbox{450} hbox{nm}$ and 650–700 nm) From a Silicon-Based Light Source

In this letter, bright "purple" electroluminescence is observed from a multilayer stack with thin amorphous silicon (alpha-Si)/SiO₂, due to the dual-color light emissions in blue and red. Under photoexcitation, the blue emission is negligible compared with the long wavelength red emission and is only present weakly after anneal in N₂ exceeding 900degC. However, under electrical excitation, the blue becomes obviously visible and shows faster increasing rate with increased carrier injection than the red. From analysis of the samples with different alpha-Si thicknesses (2-7 nm), the red emission is deemed to have resulted from the quantum-confinement effect within the thin alpha-Si layers, whereas the blue emission is speculated to have originated from the Si/SiO₂ interfacial defects.     

Experimental evaluation of on-chip measurement of charge transferby X-rays

A new on-chip testing technique is proposed and experimentally evaluated. It is based on the diffraction of highly monochromatic and collimated X-rays of dimensions of ~1 μm from single crystal semiconductors. Small differences in electronic distribution in FETs, including 2 DEG HEMTs, CCD, or many other charge transfer concepts of monolithic integrated circuits can yield measurable X-ray intensity changes. A calculation of the sensitivity shows that charges in resonant quantum structures can also produce detectable scattering variations if there are around 500 electrons in a well of dimensions 500×500 nm ². The new technique is therefore relevant for future highly packaged ICs with near-sub-micrometre dimensions     

Optimal life testing schedule for multiple types of integratedcircuits

Life testing of highly reliable integrated circuits (ICs) is a time-consuming process because it usually takes a long time before an IC fails. Several methods have been proposed in the literature to reduce the time required for testing one type of IC. The author considers the problem of estimating the mean life of I types of IC (I>1). Assuming that the lifetime distribution of the ICs is exponential and at most N ICs can be tested concurrently, it is shown that the optimal life testing schedule that requires the smallest mean testing time is to test N ICs of type 1, then test N ICs of type 2,. . . and finally test N ICs of type I      

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

High-Work-Function Ir/HfLaO ${rm p}$-MOSFETs Using Low-Temperature-Processed Shallow Junction

We report a high effective work function (Phi_m-eff) and a very low Vt Ir gate on HfLaO p-MOSFETs using novel self-aligned low-temperature shallow junctions. This gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion using SiO₂-covered Ga or Ni/Ga. At 1.2-nm effective oxide thickness, good Phi_m-eff of 5.3 eV, low V_t of +0.05 V, high mobility of 90 cm²/V-s at -0.3 MV/cm, and small 85degC negative bias-temperature instability (NBTI) of 20 mV (10 MV/cm for 1 h) are measured for Ir/HfLaO p-MOSFETs.     

P-Channel Tri-Gate FinFETs Featuring $hbox{Ni}_{1 - y}hbox{Pt}_{y} hbox{SiGe}$ Source/Drain Contacts for Enhanced Drive Current Performance

We report the integration of nickel platinum germanosilicide (Ni_1-yPt_ySiGe) contacts in tri-gate FinFETs with silicon germanium source/drain stressors for enhanced drive current performance. The structural and electrical properties of Ni_1-yPt_ySiGe contacts with platinum (Pt) concentrations up to 20 atomic % (at. %) were explored for FinFET integration. Our results show that Ni_1-yPt_ySiGe incorporated with 10 at. % Pt shows superior morphological stability, a suitably low sheet resistivity and the lowest Schottky hole barrier height (Phi_P ^B) among the candidates evaluated. The low Phi_P ^B(0.309 eV) provides a 15% reduction in series resistance R_series. With a superior morphological stability and reduced R_series, FinFETs integrated with contacts exhibit an overall 18% improvement in drive current compared to FinFETs with NiSiGe contacts.