VLSI低功耗技术研究

功耗已成为超大规模集成电路所面临的最大技术挑战之一.这就需要在不断满足设计要求的同时,不断提出新的方法来降低功耗.文章首先概述了VLSI的功耗问题,进而提出了VLSI功耗的来源,最后提出了降低CMOS集成电路功耗的技术与方法.     

CMOS电路中外部能耗控制模块的设计与实现

传统的大规模集成电路的功耗控制方法存在运算量高、精确度有限的问题。因此,基于双阈值低功耗技术设计并实现CMOS电路中外部能耗控制模块,采用双阈值电压技术通过较低阈值的晶体管设计CMOS能耗控制模块。通过高阈值电压的NMOS管控制低阈值模块,降低电路的泄露电流,使用低阈值模块中的NMOS管对CMOS门单元电路进行管理,提高门单元电路的运行效率,降低总体CMOS电路的功耗。采用双阈值技术设计CMOS电路的单边沿脉冲触发器,对触发器的时钟响应电路进行优化,确保时钟翻转通过数字信号进行管理,极大降低时钟翻转频率,减小电路动态功耗。实验结果表明,所设计模块具有较高的控制效率,较低的延迟和功耗,其控制下的CMOS电路节能效果显著。     

冒险共振现象及其在CMOS电路最大功耗估计中的应用

随着集成电路工艺的不断提高，CMOS电路规模不断增大，功耗成为集成电路设计主要指标之一。文章首先以多位比较器为例，阐述了存在于部分多位电路功能块中的冒险共振现象；然后给出其在VLSI电路最大功耗估计中的应用。ISCAS85电路集实验结果证实了文章思路的有效性。     

基于P-PFAL的绝热乘法器漏功耗减小技术

随着超大规模集成电路的不断发展和提高,功耗问题成了集成电路设计中不可忽略的因素。本课题通过对树形乘法器和正反馈绝热逻辑(PFAL)电路工作原理的研究,提出一种四相功控基于PMOS管的PFAL绝热逻辑乘法器设计方案。在45nm工艺下通过HSPICE模拟仿真,仿真结果显示逻辑功能正确,并且这种乘法器与传统静态CMOS乘法器相比,该设计节省电路的功耗92.9%。     

低功耗方法在SoC芯片设计中的应用

SOC芯片设计在集成电路设计中占据重要位置,低功耗设计是SoC设计过程中的重要环节。本文首先全面分析了CMOS电路的功耗组成和功耗估计的相关理论,随后从各个设计层次详细分析了SOC芯片低功耗设计的理论及其实现方法。     

CMOS图像传感器的最新进展及其应用

CMOS图像传感器是20世纪70年代在美国航空航天局（NASA）的喷气推进实验室（JPL）诞生的，与CCD图像传感器几乎同步，标准CMOS大规模集成电路技术的不断发展大大改善了CMOS图像传感器的图像质量，CMOS图像传感器的高度集成化减小了系统的复杂性，降低了制造成本，仅为普通CCD图像传感器的1／20，对获得的图像信息读出及处理变得简单而快捷，能设计出灵活的小型成像系统，它具有单一工作电压，功耗低，像素缺陷率低，可与其他CMOS集成电路兼容，对局部像素的编程可随访问等优点。本文主要介绍CMOS图像传感器的发展现状，最新进展，市场前景及其在医学上的应用。     

CMOS集成电路的可俈性

CMOS集成电路具有功耗低,抗干扰力强和速度快的特点,在一般逻辑电路,大规模存贮器以及微处理机、电子手表等领域得到广泛的应用,尖端技术的发展对CMOS集成电路的可俈性提出了更高的要求,人们对其可俈性也日益重视。本文对CMOS集成电路的失效模式、机理、抗辐射性能等作一概要介绍。     

深亚微米CMOS低噪声放大器的设计

通过一个符合性能指标的，用于射频接收系统的CMOS低噪声放大性能的设计，讨论了深亚微米MOSFET的噪声情况，并在满足增旋和功耗的前提下，对低噪声放大噪声性能进行分析和优化，该LNA工作在2.5GHz电源电压，直流功耗为25mW，能够提供19dB的增益（S21），而噪声系数仅为2.5dB，同时输入匹配良好，S11为-45dB，整个电路只采用了一个片外电感使电路保持谐振，此设计结果证明CMOS工艺在射频集成电路设计领域具有可观的潜力。     

多媒体SOC芯片的低功耗设计

从集成电路功耗原理出发,分析了CMOS电路功耗的来源,从集成电路设计的系统级、算法级、架构级、电路/门级以及工艺/器件级五个抽象层次出发,整理、总结了当前主要的低功耗设计方法,并在实际的移动多媒体处理应用SOC芯片设计中,平衡产品成本、设计复杂度、设计环境等多种因素,确定并应用了适合设计对象的低功耗设计方法的组合.通过对于样片功耗的测试分析,低功耗设计方法(组合)取得了预期的效果,实现了较低的动态功耗与很低的静态功耗.     

一种适用于模/数混合集成电路的新型低噪声电流控制逻辑

本文给出了一种新型低噪声电流控制逻辑结构，用于在模／数混合集成电路的设计中取代静态CMOS逻辑，以减小数字开关噪声通过衬底耦合对模拟电路性能的影响．在分析了该逻辑的基本工作原理后，本文对电流控制逻辑的逻辑结构，开关特性，噪声特性和功耗及功耗-延迟积等性能与静态CMOS逻辑作了比较，并用电路模拟进行了验证．理论分析和电路模拟的结果都显示，和静态CMOS逻辑相比，新型电流控制逻辑的峰值噪声电流下降了近三个数量级．该逻辑具有很好的设计灵活性和低电压工作性能，并已成功地应用于一个高性能的过采样A／D转换电路中．     

Low-power/low-voltage RF microsystems for wireless sensors networks

This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.     

Sleepy Stack Leakage Reduction

Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for CMOS circuits in nanoscale technology. We propose a novel ultra-low leakage CMOS circuit structure which we call "sleepy stack". Unlike many other previous approaches, sleepy stack can retain logic state during sleep mode while achieving ultra-low leakage power consumption. We apply the sleepy stack to generic logic circuits. Although the sleepy stack incurs some delay and area overhead, the sleepy stack technique achieves the lowest leakage power consumption among known state-saving leakage reduction techniques, thus, providing circuit designers with new choices to handle the leakage power problem     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2)latch and its application in a dual-modulus prescaler

A high speed dual-phase dynamic-pseudo NMOS ((DP)²) latch using clocked pseudo-NMOS inverters is presented. Compared to the conventional D-latch, this circuit has a higher maximum operating frequency and consumes lower dynamic power at a given operating frequency. The latch has been demonstrated by utilizing it in the synchronous counter section of a dual-phase dual-modulus prescaler implemented in a 0.8 μm CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the power consumption is 9.7 mW. This power consumption is significantly lower than those of the previously reported prescalers implemented in 0.8 μm CMOS processes. The 9.7 mW power consumption at 1.3 GHz also compares favorably to the 24 mW power consumption of the 1.75 GHz prescaler using MOS current mode latches implemented in a 0.7 μm CMOS process. A 25% reduction of the maximum operating frequency for a ~60% reduction of the power consumption should be a useful tradeoff     

Genetic algorithm-based FSM synthesis with area-power trade-offs

Traditionally, state-encoding strategies targeting minimization of area, dynamic power or a combination of them have been utilized in finite state machine (FSM) synthesis. With drastic scaling down of devices at recent technology level, leakage power has also become an important design parameter to be considered during synthesis. A genetic algorithm-based state encoding, targeting area and power minimized FSM, has been proposed in this paper. A unified technique to reduce both static power (leakage) and dynamic power along with area trade-off has been carried out for FSM synthesis, targeting static CMOS NAND-NAND PLA, dynamic CMOS NOR-NOR PLA and pseudo-NMOS NOR-NOR PLA implementations. Suitable weights for area, leakage power and dynamic power to minimize power density have also been explored. Simulation with MCNC benchmarks shows an average improvement of 31%, 26% and 29% in leakage power consumption, dynamic power consumption and area requirement respectively, over NOVA-based state assignment technique in case of dynamic CMOS PLA implementation. Improvements of 30% in leakage power and 15% in area have been obtained for pseudo-NMOS PLA implementation. For the static CMOS case, the improvements are about 29% in leakage power consumption, 14% in dynamic power consumption and 18% in area requirement.     

低功耗CMOS逻辑电路设计综述

分析了ＣＭＯＳ逻辑电路的功耗来源从降低电源电压、减 上负载电容和逻辑电路开关活动几率等方面论述了降国耗的途径。讨论了深亚微米器件中亚同值电流对功耗的影响以及减小亚阈值电流的措施,最后分析了高层次设计对降低功耗的关键作用,说明低功耗设计必须从设计的各个层次加在考虑,实现整体优化设计。     

一种低温漂的CMOS带隙基准电压源的研究

为了满足深亚微米级集成电路对低温漂、低功耗电源电压的需求,提出了一种在0.25μm N阱CMOS工艺下,采用一阶温度补偿技术设计的CMOS带隙基准电压源电路。电路核心部分由双极晶体管构成,实现了VBE和VT的线性叠加,获得近似零温度系数的输出电压。T-SPICE软件仿真表明,在3.3 V电源电压下,当温度在-20~70℃之间变化时,该电路输出电压的温度系数为10×10-6/℃,输出电压的标准偏差为1 mV,室温时电路的功耗为5.283 1 mW,属于低温漂、低功耗的基准电压源。     

Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout

In this paper the power consumption and power integrity of a CMOS ring oscillator has been analysed when their pFETs are subjected to negative bias temperature instability (NBTI). The impact of pFET under NBTI has been experimentally quantified whereas CMOS ring oscillator power consumption and power integrity have been evaluated by means of electrical full-model simulation. The results show that power consumption is reduced and power integrity remains constant with NBTI wearout..     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.