Optimisation des performances de modules multipuces Modélisation par réseaux de neurones

Widely used in microwave multichip module design, passive device models are subject to intensive researches. This paper introduces the concept of automate generation of neural models for passives and interconnects. Accurate and fast, these models efficiently integrate electromagnetic effects present at microwave frequencies. By optimizing the circuit performance, the proposed approach can automatically predict not only the final geometrical structure of the different passive components and their respective interconnects but also, for the fist time, their optimum location in the circuit. Applications using passive models implemented in circuit simulators are presented.     

Analytical Models of Passive Linear Structures in Printed Circuit Boards

Analytical models for passive linear structures, like metallic traces, vias, are proposed for simulations at the package and Printed circuit board (PCB) levels. In the proposed method, traces are modeled based on the transmission line theory, whereas the vias are described by the parallel-plate impedance and several equivalent circuits elements. The proposed models can be applied to efficiently simulate composed passive linear structures. Several scenarios are analyzed including traces with two or three width, traces routed into different layers and interconnects commonly used in PCBs. The results of the models are compared with those from the full-wave simulations and experiments. An improvement on the computation speed has been observed with respect to the full-wave simulations at the effective range of models. In our measurements, a compensation approach of impedance mismatch in parameter measurements is analyzed and calculated, which could significantly simplify the experimental process.     

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

Pole-residue formulation for transient simulation of high-frequencyinterconnects using householder LS curve-fitting techniques

As digital circuits approach the GHz range, and as the need for high performance wireless devices increases, new simulation tools which accurately characterize high frequency interconnects are needed. In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented. The algorithm incorporates Householder LS curve-fitting techniques. The approach generates a universal macromodeling tool that enables simulation of interconnects in a modified version of simulation program with integrated circuit emphasis (SPICE). This results in a method that conveniently incorporates accurate EM models of interconnects or experimental data into a circuit simulator. The time domain simulation results using this new tool are compared with results from other simulators     

Improved global rational approximation macromodeling algorithm fornetworks characterized by frequency-sampled data

Recently, the demand for high-performance wireless designs has been increasing while simultaneously the speed of high-end digital designs have crossed over the gigahertz range. New simulation tools which accurately characterize high-frequency interconnects are needed. This paper presents improvements to a new macromodeling algorithm. The algorithm employs curve-fitting techniques to achieve a pole-residue approximation of the frequency-sampled network. The frequency sampled S-parameters or Y-parameters can be obtained from measurement or full-wave simulation to characterize the frequency-dependent interconnects behavior. The improvements extend the approach to lossless structures, increase its accuracy with pole-clustering, and ensure its validity with a passivity test. This paper addresses some of the special considerations that must be made to the method so it can efficiently and accurately be applied to lossless circuits and structures. The resulting algorithm is now capable of accurately extracting a wide-band frequency domain macromodel from frequency-sampled data for either LC circuit (lossless) or RLC circuits (lossy). The frequency-domain macromodel can be linked to a SPICE circuit simulator for mixed signal circuit analysis using RF, analog, and digital circuits. The circuit can be simulated in the time domain using recursive convolution     

Broadband Rational Macromodeling Based on the Adaptive Frequency Sampling Algorithm and the Partial Element Equivalent Circuit Method

The increasing operating frequencies in modern designs call for broadband macromodeling techniques. The problem of computing high-accuracy simulation models for high-speed interconnects is of great importance in the modeling arena. Nowadays, many full-wave numerical techniques are available that provide high accuracy, often at a significant cost in terms of memory storage and computing time. Furthermore, designers are usually only interested in a few electrical quantities such as port voltages and currents. So, model order reduction techniques are commonly used to achieve accurate results in a reasonable time. This paper presents a new technique, based on the partial element equivalent circuit method, which allows to generate reduced-order models by adaptively selecting the complexity (order) of the macromodel and suitable frequency samples. Thus, the proposed algorithm allows to limit the computing time while preserving the accuracy. Validation examples are given.     

Hierarchical Krylov subspace based reduction of large interconnects

In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and the Krylov subspace projection-based model order reduction methods. The new approach, called hiePrimor, first partitions a large interconnect circuit into a number of smaller subcircuits and then performs the projection-based model order reduction on each of subcircuits in isolation and on the top-level circuit thereafter. The new approach is very amenable for exploiting the multi-core based parallel computing platforms to significantly speed up the reduction process. Theoretically we show that hiePrimor can deliver the same accuracy as the flat reduction method given the same reduction order and it can also preserve the passivity of the reduced models as well. We also show that partitioning has large impacts on the performance of hierarchical reduction and the minimum-span objective should be required to attain the best performance for hierarchical reduction. The proposed method is suitable for reducing large global interconnects like coupled bus, transmission lines, large clock nets in the post-layout stage. Experimental results demonstrate that hiePrimor can be significantly faster and more scalable than the flat projection methods like PRIMA and be order of magnitude faster than PRIMA with parallel computing without loss of accuracy. Interconnect circuits with up to 4 million nodes can be analyzed in a few minutes even in Matlab by the new method.     

PEEC Modeling of Dispersive and Lossy Dielectrics

In this paper a general formulation is presented for the time-domain partial element equivalent circuit method in a general dispersive medium. The formulation is based on Debye and Lorentz models where the resulting model is passive. The incorporation of such models into a partial element equivalent circuit solver is described by both convolution techniques and equivalent circuits. The new circuit models can be applied in the frequency as well as the time domain. Numerical examples are given to validate the proposed formulation and to show that the proposed method is accurately capturing the physics of dispersive and lossy dielectrics.      

High-speed interconnects with underlayer orthogonal metal grids

On-chip high-speed interconnects with underlayer orthogonal metal grids, including grid-backed lines (GBLs) and grid-backed coplanar waveguides (GBCPWs), are characterized through s-parameter measurements. For GBL test structures, the presence of underlayer metal grids reduces dispersion by a factor of 4 while the local speed of light decreases by a factor of 2 in comparison to those of conventional microstrip lines. The dispersion reduction comes from suppressing higher order modes; the local speed of light reduction comes from a longer current return path. These characteristics are beneficial for compact CMOS analog circuit designs. Losses caused by substrate and conductor lines are restrained by shielding the substrate and by involving weaker electric fields. Resonance at a frequency characterized by that of a patch antenna was observed and needs to be considered in high-speed circuit designs. The grids have weaker effects in the case of CPWs, where the side ground plate effects are significant. A signal transmission example shows that dispersion and frequency-dependent losses are important in determining the signal rise edge. Semi-empirical distributed resistance-inductance-capacitance-conductance (RLCG) equivalent circuit models are constructed for the interconnects below the resonant frequencies.     

Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods

This paper introduces an efficient and passive discrete modeling technique for estimating signal propagation delays through on-chip long interconnects that are represented as distributed RLC transmission lines. The proposed delay model is based on a less frequently used numerical approximation technique, called the differential quadrature method (DQM). The DQM can compute the partial derivative of a function at any arbitrary point located within a prespecified closed domain of the function by quickly estimating the weighted linear sum of values of the function at a relatively small set of well-chosen grid points within the domain. By using the fifth-order DQM, a new approximation framework is constructed in this paper for discretizing the distributed RLC interconnect and thereafter modeling its delay. Due to high efficiency of DQM approximation, the proposed framework requires only few grid points to achieve good accuracy. The presented equivalent-circuit model appears like the ones derived by the finite difference (FD) method. However, it has higher accuracy and less internal nodes than generated by the FD-based modeling. The fifth-order DQM modeling technique is shown to preserve passivity. It has linear forms that are compatible with the passive order-reduction algorithm for linear network. Numerical experiments show that the proposed modeling approach leads to high accuracy as well as high efficiency.     

A practical approach to model long MIS interconnects in VLSI circuits

In this paper, a practical approach to model metal-insulator-semiconductor (MIS) interconnects is presented, with focus on the microstrip configuration. Starting from a one-dimensional (1-D) electromagnetic field analysis, we first extend the validity range of some closed-form expressions from 1-D to two-dimensional (2-D) and present an original RLCG-B model with five equivalent circuit parameters. These parameters, which depend on two effective widths of the physical metal strip, can be frequency dependent because of the skin effect and the dielectric losses. The original RLCG-B model is then modified and implemented with seven frequency-independent circuit parameters. These parameters are computed by analytical equations. Numerical simulations are used to validate the original and modified RLCG-B models. A formula to allow comparison of various interconnect models in the time domain is proposed. Comparisons based on this formula are presented for a single transmission line with source resistance, R/sub S/, and load capacitance, C/sub L/. Such comparisons are more meaningful in VLSI applications than comparisons of characteristics derived from swept-frequency per-unit-length parameters.     

Models and Tools for CMOS Integrated Inductors

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.     

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm² cross-sectional area     

Model order reduction using spline-based dynamic multi-point rational interpolation for passive circuits

The efficient modeling of integrated passive components and interconnects is vital for the realization of high performance mixed-signal systems. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order models for passive components and interconnects that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply uniform interpolation points.     

Circuit models for three-dimensional geometries includingdielectrics

The partial element equivalent circuit (PEEC) approach has proved useful for modeling many different electromagnetic problems. The technique can be viewed as an approach for the electrical circuit modeling for arbitrary 3-D geometries. Recently, the authors extended the method to include retardation with the rPEEC models. So far the dielectrics have been taken into account only in an approximate way. In this work, they generalize the technique to include arbitrary homogeneous dielectric regions. The new circuit models are applied in the frequency as well as the time domain. The time solution allows the modeling of VLSI systems which involve interconnects as well as nonlinear transistor circuits     

Compact HSPICE model for IMOS device

A compact HSPICE model has been developed for the newly proposed impact-ionisation MOS (IMOS) device for circuit simulation. Table lookup dependent sources and passive components have been employed to model the IMOS device. The approach shows good accuracy compared to time-consuming and non-scalable TCAD simulation of IMOS-based circuits.     

Time-domain modeling of high-speed interconnects by modified methodof characteristics

In this paper, a new model of lossy transmission lines is presented for the time-domain simulation of high-speed interconnects. This model is based on the modified method of characteristics (MMC). The characteristic functions are first approximated by applying lower order Taylor series in the frequency domain, and then a set of simple recursive formulas are obtained in the time domain. The formulas, which involve tracking performances between two ends of a transmission line, are similar to those derived by the method of characteristics for lossless and undistorted lossy transmission lines. The algorithm, based on the proposed MMC model, can efficiently evaluate transient responses of high-speed interconnects. It only uses the quantities at two ends of the lines, requiring less computation time and less memory space than required by other methods. Examples indicate that the new method has high accuracy and is very efficient for the time-domain simulation of interconnects in high-speed integrated circuits     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

A novel systematic approach for equivalent model extraction of embedded high-speed interconnects in time domain

Based on time-domain scattered data, an efficient systematic approach in the time domain has been proposed to extract the SPICE-compatible models of embedded high-speed interconnects. The approach combines the layer-peeling technique and the generalized pencil-of-matrix method to obtain a pole-residue representation of the step response of the interconnects. An order-reduction procedure is implemented based on the bandwidth criterion to find the optimum pole-residue representation of the interconnects with minimum pole numbers. The SPICE-compatible lumped circuits are then systematically extracted from the pole-residue rational functions. The discontinuous microstrip lines and bonding wire structure are used to demonstrate the validity of the proposed approach. Good agreement is seen between the modeled and measured transient response. The advantages of this approach are the de-embedding ability for arbitrary nonuniform interconnects, systematically obtaining lower order and more accurate SPICE-compatible circuits, and broad-band performance of the extracted circuits.