Synthesis of indium nanoclusters and formation of thin film contacts on plastic substrates for organic and flexible electronics applications

In this work, we described the processes of synthesizing free-standing indium nanoclusters using inverse micelles and microemulsions as well as synthesizing organic-encapsulated indium nanoclusters using alkanethiols as the organic encapsulants. The synthesized organic-encapsulated indium nanoclusters have demonstrated the feasibilities to be used as plastic compatible soft metal contacts for emerging organic devices. The homogeneously distributed indium nanoclusters with sizes of 10-30?nm have been fabricated on a few different plastic substrates. By changing the alkanethiol carbon chain length and the sizes of the indium nanoclusters, the annealing temperature required to form low-resistance indium thin film conductors has been reduced to 80-100?°C, which is acceptable for a variety of organic thin films.     

Fabrication of poly-silicon nano-wire transistors on plastic substrates

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150 degrees with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.     

Life tests on CdSe thin film transistors

CdSe thin film transistors have been subjected to “shelf” life tests atelevated temperatures. It was found that the characteristics showed an initial deterioration followed by a recovery within 200 h, after which they exhibited good stability. A mechanism to account for this behaviour is tentatively proposed.     

Materials analysis of thin film transistors

The structure of vapour-deposited CdSe films was found to be random. However, on annealing, grain growth occurred with the basal plane parallel to the plane of the film. The crystal structure indexed to the hexagonal Wurtzite form but substrate defects resulted in non-uniformity of the film and the CdSe in these regions contained a strong component of grains oriented with the basal planes perpendicular to the films. In addition the larger grains produced by grain growth contained a high density of planar faults probably as a result of stacking disorder.The chromium contact pad used in thin film transistor devices is not stable. During the annealing process chromium diffuses laterally into the CdSe producing circumferential regions of different grain size. Also there is a reaction between chromium and CdSe resulting in the formation of columnar grains of chromium-deficient chromium selenide and the release of elemental cadmium.     

Characteristics of laser-annealed ZnO thin film transistors

We investigated the effects of laser annealing on ZnO thin film transistors (TFTs). ZnO layers were deposited on a bottom-gate patterned Si substrate by radio-frequency sputtering at room temperature. Laser annealing of the ZnO films reduced the full width at half maximum of the ZnO (002) diffraction peak from 0.49° to 0.1°. It reveals that the crystalline quality is improved by annealing effect. A SiO₂ formed in low temperature was used as the gate dielectric. Unannealed ZnO-TFTs were operated in enhancement mode with a threshold voltage of 21.6 V. They had a field-effect mobility of 0.004 cm²/Vs and an on/off current ratio of 134. Laser annealing of the ZnO-TFTs by 200 laser pulses reduced their threshold voltage to 0.6 V and increased their field-effect mobility to 5.08 cm²/Vs. The increase of mobility is originated from the crystallization enhancement of ZnO films after laser annealing.     

CuInGaSe2 (CIGS) thin film on flexible Mo substrates from non-aqueous one-step electrodeposition process

CuInGaSe₂ (CIGS) thin films have been potentiostatically electrodeposited from the non-aqueous electrolyte bath at 130 °C onto flexible molybdenum foil. The deposition potential for the quaternary CIGS layer was optimized using cyclic voltammetry measurements. The samples were electrodeposited at ? 0.8 and ? 1.1 V with respect to the Ag/AgCl reference electrode and subsequently annealed with rapid thermal processing. The samples were characterized for the structural, optical morphological, and compositional properties using a range of characterization techniques. RTP annealed samples show a significant improvement in crystallinity and particle size. XRD results revealed the three prominent reflections of chalcopyrite CIGS corresponds to (112), (204)/(220), and (116)/(312) reflection of a tetragonal crystal structure. The prominent peak exhibit in Raman spectra at 174 cm^?1 corresponds to the A₁ mode symmetry of the CIGS chalcopyrite phase. The optical energy band gap is estimated to be?~?1.12 and 1.35 eV for annealed samples deposited at ? 0.8 V and ? 1.1 V, respectively. SEM images confirmed the growth of uniform void-free and densely packed thin layer suitable for the CIGS thin-film solar cell. Electrical studies show the improvement in the ideality factor and carrier concentration in the RTP annealed samples. It was further found that the deposition potential plays an important role to control the stoichiometry and uniformity of the samples.

     

Non-aqueous solution processed ZnO thin film transistors

Zinc oxide based thin film transistors (TFT) fabricated by a non-aqueous sol-gel solution process with a zinc neodecanoate precursor are demonstrated. X-ray diffraction measurement reveals that the ZnO films adopt a hexagonal structure with a random crystal orientation. Atomic force microscope and scanning electron microscope characterizations show that the films are closely packed and consisted of particles with an average size of 45 nm. The devices exhibit an n-channel enhancement mode behavior, with saturation mobility in the range of 0.95-1.29 cm² V⁻¹ s⁻¹, drain current on-to-off ratios higher than 10⁷ and threshold voltages between 5.3 and 16.8 V in an ambient environment. The results imply that high-performance ZnO TFTs produced by a simple and low-cost technique could be applicable to electronic devices.     

光学塑料棱镜反射膜的镀制

由于光学塑料在耐热性、耐吸湿性和表面强度等方面的特性比光学玻璃差,所以在光学塑料棱镜表面上镀制金属反射膜存在着金属膜层和塑料棱镜表而附着性能差的问题,镀膜后的塑料棱镜不易达到使用的技术要求.本文通过对镀膜材料和光学塑料基体的特性分析,提出了一种实用的介质加金属三层反射膜系.基于这种膜系采用了等离子辅助镀膜技术和石英晶片监控膜厚的方法,并且针对塑料棱镜蒸镀的特殊性,严格控制蒸镀条件中的有关参数,形成了一套稳定的蒸镀工艺.实验结果表明,光学塑料棱镜镀制金属反射膜可以解决膜层性能差的问题,满足光学产品的技术要求,实现批量生产.     

Mechanical failure analysis of thin film transistor devices on steel and polyimide substrates for flexible display applications

The crack onset strain (COS) of 4-level thin film transistor (TFT) devices on both steel foils and thin polyimide (PI) films was investigated using tensile experiments carried out in situ in an optical microscope. Cracks initiated first within the SiO₂ insulator layer for both types of substrates. The COS was found to be equal to 1.15% and 0.24% for steel and PI, respectively. The influence of loading direction on failure of the TFT stack with anisotropic geometry was moreover found to be considerable, leading to recommendations for backplane design. The large difference in critical strain of the SiO₂ layer on the two substrates was analyzed using an energy release rate approach, and found to result from differences in layer/substrate mechanical contrast and in internal stress state. Based on this analysis a correlation between layer/substrate elastic contrast and tensile failure behavior was devised.     

Nanometer-scale organic thin film transistors from self-assembled monolayers

A survey of the most interesting results on nanometer-scale organic thin film transistors (nano-OTFT) is presented. Additionally, we discuss our recent results on the properties of end-group functionalized organic self-assembled monolayers and on their use in the fabrication of nanometer-scale field-effect transistors. Nanometer-scale organic transistors (channel length 30 nm) were fabricated, with a self-assembled monolayer as gate insulator. The carrier transport in these transistors, as a function of the channel length, was investigated, and a transition from a dispersive to a ballistic transport at a channel length of 200 nm was observed. On a molecular scale, alkyl monolayers functionalized at their omega-ends by aromatic moieties were prepared. A high anisotropic conductivity in molecular insulator/semiconductor heterostructures of monolayer thickness was observed. These molecular architectures provide a basis for the building blocks of molecular transistors.     

Nitrogen-added Al rare-earth alloys for thin film transistors

The effects of nitrogen addition to aluminum-rare-earth alloys were investigated. Yttrium and gadolinium were employed as respective alloy components. The electrical properties and hillock densities of alloy films were investigated, and their nanostructures were studied by cross-sectional transmission electron microscopy. Nitrogen effectively decreases the grain size, and causes the columnar structure, that is generally present in aluminum-based alloys, to disappear. Nitric aluminum-rare-earth alloys have a strong resistance to hillock formation, and formed no micro-voids even after annealing at 450°C. An N₂ flow rate of 1.3–10% in the sputtering gas gives a low hillock density of 2.0E+1–7.7E−1 pcs/mm² after annealing at 350°C in both nitric Al-rare-earth alloys. In the case of patterned nitric aluminum-yttrium alloys, an N₂ flow rate of less than 1.3% causes large side-hillocks after annealing at over 350°C. As an optimum value, an N₂ flow rate of 2.5% results in a low hillock density of 1.9E+1 pcs/mm² and a low resistivity of 8.6 μΩ cm after annealing at 350°C.     

氧化亚锡薄膜晶体管的研究进展EI北大核心CSCD

p型金属氧化物材料氧化亚锡由于其特有的光学和电学性能,使得其在催化、传感、光电器件等领域受到越来越多人的青睐。本文重点介绍了氧化亚锡在薄膜晶体管中的研究应用,薄膜晶体管作为显示器驱动面板核心部件,其在显示器中的作用至关重要。本文归纳了氧化亚锡薄膜晶体管的研究进展,对氧化亚锡微观性能分析、氧化亚锡薄膜材料制备以及晶体管制备方法等进行介绍。通过对氧化亚锡晶体结构以及电子结构进行详细介绍,探讨了氧化亚锡性能微观调控机制;并通过对氧化亚锡材料的制备以及器件的应用研究,分析了氧化亚锡薄膜晶体管所面临的器件电流开关比低的问题并展望其在互补金属氧化物半导体器件方向的前景,以期为制备稳定和环保的p型金属氧化物薄膜晶体管提供参考。     

Hydrogenation of nanocrystalline Si thin film transistors employing inductively coupled plasma chemical vapor deposition for flexible electronics

We have investigated the plasma hydrogenation effect on a nanocrystalline silicon (nc-Si) thin film transistor (TFT) fabricated by inductively coupled plasma chemical vapor deposition (ICP-CVD) at 150 °C. The top-gate nc-Si TFT showed a mobility of ∼ 6 cm²/Vs and V_th of 8 V. The hydrogenation employing ICP-CVD was performed at 100 °C for 4 min in order to improve the characteristics of nc-Si TFT. The mobility was increased from ∼ 6 cm²/Vs to 11 cm²/Vs. The V_th of the nc-Si TFTs was decreased to about 6.8 V from 8.1 V. The on-current at the saturation regime also increased by 66% while the off current was increased slightly. The improvement of mobility, threshold voltage and on-current can be attributed to the hydrogen passivation of the Si dangling bonds in the nc-Si film. The experimental results showed that the 100 °C ICP-CVD hydrogenation is effective to improve the 150 °C nc-Si TFT.     

Peak channel temperature of graphene-based transistors

In this study, graphene was mechanically deposited on SiO2/Si substrate, followed by ohmic metallization using electron-beam lithography. Finite element analysis was employed to characterize the operating temperature of graphene-based devices using the experimentally determined current-voltage data. The temperature of the hottest spot where the underlying SiO2 layer was 300 nm thick was elevated up to about 70 degrees C at a 10 mW dissipated power. However, the operating temperature dropped to about 50 degrees C when the 300 nm thick SiO2 layer was replaced with a 20 nm thick SiO2 layer. Thermal management is very critical in the reliability of graphene-based high speed electronic devices because the high operating temperature can degrade the device performance.     

Demagnetization-free longitudinal recording on flexible thin film metal media

The variation of demagnetization effects with media parameters for longitudinal contact recording has been investigated. Co-Re thin film metal media were sputtered onto flexible polyimide substrates. It was found that when the film thickness δ and demagnetizaton parameterB_{r}delta/H_{c}were less than 2 μ inch and 15 μinch, respectively, demagnetization-free longitudinal recording was obtained up to the recording density of 75 KFRPI at the head-to-medium spacing of 3 μ inch. As a result, recording densities of D50over 50 KFRPI were achieved with a 20 μinch gap head. For thicker films with larger demagnetization parameters, i.e.,delta geq 4 muinch andB_{r}delta/H_{c} geq 40 muinch, the longitudinal recording process approached the demagnetization limit. The results show that (with existing head field gradients) improvement in linear density of thin metal media can be obtained by an approximate factor of two before the demagnetization limit is reached.     

Electro-fragmentation analysis of dielectric thin films on flexible polymer substrates

An electro-fragmentation method was developed as a fast alternative to the time consuming fragmentation test carried out in situ in a microscope, to investigate the failure of dielectric inorganic coatings on polymer substrates. An ultrathin conductive layer was used to probe the onset of tensile failure in the dielectric coating through changes of its electrical resistance. A careful selection of the conductive layer has been carried out to avoid artifacts resulting for instance from a change of the cohesive properties (e.g. internal stress state) of the investigated structures. Au layers were found to be too ductile, contrary to Al-Ti layers that were too brittle, which invalidated the use of both materials to probe the failure of the dielectric coatings. In contrast, for structures on high-temperature polymer substrates, a 10 nm thick amorphous graphite (a-G) layer was found to accurately reproduce the cracking of the coating. The Young's modulus and coefficient of thermal expansion of the a-G layer are low enough not to impact the internal strain, hence the crack onset strain of the dielectric coating. The a-G layer is also sufficiently brittle, and its cohesive failure and resulting increase of electrical resistance is triggered by the failure of the dielectric coating. The a-G electro-fragmentation method is presently limited to polymers substrates with a glass-transition temperature higher than 100 °C.     

Length-sorted semiconducting carbon nanotubes for high-mobility thin film transistors

We have developed a process for chemical purification of carbon nanotubes for solution-processable thin-film transistors (TFTs) having high mobility. Films of the purified carbon nanotubes fabricated by simple drop coating showed carrier mobilities as high as 164 cm²V⁻¹s⁻¹, normalized transconductances of 0.78 Sm⁻¹, and on/off current ratios of 10⁶. Such high performance requires the preparation of a suspension of micrometer-long and highly purified semiconducting single-walled carbon nanotubes (SWCNTs). Our purification process includes length and electronic-type selective trapping of SWCNTs using recycling gel filtration with a mixture of surfactants. The results provide an important milestone toward printed high-speed and large-area electronics with roll-to-roll and ink-jet device fabrication.