微系统与中规模器件的封装技术设计

文章主要论述了微机电系统(MEMS)和微系统诸如微传感器、驱动器和微流体元件的电机封装技术、封装等级和封装技术相关的问题.首先陈述并讨论了典型的MEMS产品诸如微压传感器、加速度计和微泵;微电子封装和微系统封装技术,重点阐述芯片级封装技术和器件级封装技术问题.芯片级封装技术主要涉及芯片钝化、芯片隔离和芯片压焊;器件级封...     

芯片叠层封装工艺技术研究

随着大量电子产品朝着小型化、高密度化、高可靠性、低功耗方向发展,将多种芯片封装于同一腔体内的芯片叠层封装工艺技术将得到更为广泛的应用,其封装产品的特点就是更小、更轻盈、更可靠、低功耗。芯片叠层封装是把多个芯片在垂直方向上堆叠起来,利用传统的引线封装结构,然后再进行封装。芯片叠层封装是一种三维封装技术,叠层封装不但提高了封装密度,降低了封装成本,同时也提高了器件的运行速度,且可以实现器件的多功能化。随着叠层封装工艺技术的进步及成本的降低,多芯片封装的产品将更为广泛地应用于各个领域,覆盖尖端科技产品和应用广大的消费类产品。     

电子元器件封装技术发展趋势

晶圆级封装、多芯片封装、系统封装和三维叠层封装是近几年来迅速发展的新型封装方式,在推动更高性能、更低功耗、更低成本和更小形状因子的产品上,先进封装技术发挥着至关重要的作用。晶圆级芯片尺寸封装(WCSP)应用范围在不断扩展,无源器件、分立器件、RF和存储器的比例不断提高。随着芯片尺寸和引脚数目的增加,板级可靠性成为一大挑战。系统封装(SIP)已经开始集成MEMS器件、逻辑电路和特定应用电路。使用TSV的三维封装技术可以为MEMS器件与其他芯片的叠层提供解决方案。     

中国电子科技集团公司第十三研究所光电产品推介

中国电子科技集团公司第十三研究所从事半导体光电材料、光电芯片及器件研制与生产30余年。专业部具有单晶衬底、材料外延、芯片、封装、应用全产业链技术及产品研发与生产能力,拥有3英寸和4英寸均兼容的专用光电芯片工艺线、大功率半导体激光器封装工艺线和先进完善的检验检测设备,能满足多种光电芯片及器件的科研生产。现有产品包含功率激光器芯片、光通信激光器芯片、光通信探测器芯片。     

未来微处理器的封装技术--新型无凸点叠层封装

无凸点叠层(BBUL)封装技术是Intel公司研制出的1种新型封装技术,用以满足未来微处理器封装技术的要求.这种BBUL封装技术具有巨大的优越性,它免除了大多数高性能的倒装芯片所用的大量焊料凸点和互连,使环路电感量小、热机械应力小,不但减小芯片连接的寄生效应,而且提高了微处理器芯片的效率.此外,该封装的体积比传统封装更小、更轻,使多芯片之间的互连更为紧密.特别适合于高引出端的电子类及光电子产品,如逻辑单元、存储器、射频器件以及微型机电一体化系统.本文主要从其发展背景、工艺及特性方面阐述这种新型BBUL封装技术,最后提出一些建议.     

一种新型的BBUL封装技术

无凸点叠层封装（BBUL）技术是Intel公司研制出的一种新型封装技术，用以满足未来微处理器封装技术的要求。这种BBUL封装技术具有很大的优越性，它免除了大多数高性能的倒装芯片所用的大量焊料凸点和互连，使环路电感量小、热机械应力小，不但减小芯片连接的寄生效应，而且提高了微处理器芯片的效率。此外，该封装的体积比传统封装更小、更轻，使多芯片之间的互连更为紧密。特别适合于高引出端的电子类及光电子产品，如逻辑单元、存储器、射频器件以及微型机电一体化系统。本文主要从其发展背景、工艺及特性方面，来阐述这种新型的BBUL封装技术，最后提出一些建议。     

压接式GCT封装的热特性分析

电力半导体器件的散热性能和热可靠性与其封装结构密切相关,选择合适的封装结构对改善器件的散热性能和提高热可靠性非常重要。文中根据压接式GCT器件封装结构特点,采用ANSYS软件利用有限元法分析了单芯片封装和多芯片封装结构的温度及热机械应力分布,并与常规的焊接式封装进行了对比。结果表明,压接式封装结构的散热效果比焊接式封装结构稍差,但其芯片上产生的热机械应力明显减小。多芯片封装采用常规的风冷散热器时芯片温度已经超过了器件的安全工作温度(125℃),应该采用热管散热器才能保证器件可靠地工作。     

未来微处理器的封装技术—8新型无凸点叠层封装

无凸点叠层（BBUL）封装技术是Intel公司研制出的1种新型封装技术，用以满足未来微处理器封装技术的要求，这种BBUL封装技术具有巨大的优越性，它免除了大多数高性能的倒装芯片所用的大量焊料凸点互连，使环路电感量小，热机械应力小，不但减小芯片连接的寄生效应，而且提高了微处理器芯片的效率，此外，该封装的体积比传统封装更小，更轻，使多芯片之间的互连更为紧密，特别适合于高引出端的电子类及光电子产品，如逻辑单元，存储器，射频器件以及微型机电一体化系统。本主要从其发展背景，工艺及特性方面阐述这种新型BBUL封装技术，最后提出一些建议。     

微电子封装业在我国的发展

我国应积极发展微电子封装业 微电子器件是由芯片和封装通过封装工艺组合而成,因此封装是微电子器件的两个基本组成部分之一。封装为芯片提供信号和电源的互连,提供散热通路和机械、环境保护。随着微电子技术的发展,微电子器件的高频性能、热     

SAW器件封装技术概述

小型化和多功能化是SAW器件发展的主要动力,回顾了SAW器件封装的发展历史,介绍了金属封装、塑料封装、SMD封装各自的特点,详述了芯片倒装技术及芯片尺寸SAW封装技术,将通用芯片倒装技术和SAW封装的特点结合,使封装尺寸减小到极限,对今后的复合封装进行了展望。     

波导腔体用微波开关二极管封焊工艺的改进

从器件的芯片结构及封焊工艺入手，分析了封焊工艺影响成品率的各种原因，并采取相应的改进措施，提高了器件的成品率。     

多个叠层芯片封装技术

叠层芯片封装在与单芯片具有的相同的轨迹范围之内,有效地增大了电子器件的功能性, 提高了电子器件的性能。这一技术已成为很多半导体公司所采用的最流行的封装技术。文章简要叙述了叠层芯片封装技术的趋势、圆片减薄技术、丝焊技术及模塑技术。     

An embedded overlay concept for microsystems packaging

An embedded overlay concept for packaging hybrid components containing microelectromechanical systems (MEMS) is described. This packaging process is a derivative of the chip-on-flex (COF) process currently used for microelectronics packaging. COF is a high performance, multichip packaging technology in which die are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components. A laser ablation process has been developed which enables selected areas of the COF overlay to be efficiently ablated with minimal impact to the packaged MEMS devices. Analysis and characterization of the ablation procedures used in the standard COF process was performed to design a new procedure which minimized the potential for heat damage to exposed MEMS devices. The COF/MEMS packaging technology is well-suited for many microsystem packaging applications such as micro-optics and radio frequency (RF) devices.     

Applications of infrared microscopy to IC and MEMS packaging

A high sensitivity, infrared (IR) microscope operating in the wavelength range 800 to 2500 nm has been applied to a variety of packaging related issues. Applications can be divided into three categories. 1) For flip chip devices the advantage of the IR microscope is that most silicon is effectively transparent at wavelengths greater than 1100 nm. This enable defects such as voids, delamination cracks and corrosion to be investigated while the chip is mounted on the substrate. 2) The IR microscope enables thermal images of devices to be obtained with a temperature resolution of approximately 1 K and spatial resolution of 2-3 /spl mu/m. 3) The transparency of silicon to IR radiation has proved particularly valuable for characterising micro-electro-mechanical systems (MEMS) devices such as microphones, at various stages of packaging, e.g., after die bonding and wire bonding.     

叠层CSP芯片封装热应力分析与优化

对四层叠层CSP（SCSP）芯片封装器件,采用正交试验设计与有限元分析相结合的方法研究了芯片和粘结剂——8个封装组件的厚度变化在热循环测试中对芯片上最大热应力的影响．利用极差分析找出主要影响因子并对封装结构进行优化。根据有限元模拟所得结果．确定了一组优选封装结构,其Von Mises应力值明显比其它组低,提高封装器件的可靠性。     

满足各种挑战的WCSP封装持续增长

晶圆级芯片尺寸封装（WCSP）消除了类似传统的芯片键合、引线键合和倒装芯片贴装过程的封装工序。这种办法可以为半导体产品用户实现更快的上市时间。WCSP封装应用空间正在扩大到新的领域,并根据管脚数量和器件类型进行细分。WCSP封装正在集成无源、分立元件、射频和存储器器件方面得到应用,并扩展到逻辑集成电路和MEMS器件。但伴随着这种应用的增长出现了很多问题,其中包括随着芯片尺寸和管脚数量的增长对电路板可靠性的影响。概述当今的挑战,以及这些集成和硅通孔技术的未来趋势。     

Evaluation of Packaging Effect on MEMS Performance: Simulation and Experimental Study

The thermal cure required for die attach during microelectro-mechanical systems (MEMS) packaging causes thermal mismatch that induces undesirable stresses and strains in surface micromachined structures, which may adversely affect the performance and reliability of the packaged component. Understanding the influence of the packaging process is, therefore, critical for successful device design. This paper analyzes the influence of the die attach process on the electromechanical behavior of doubly-anchored surface micromachined beams. A number of different adhesive materials were considered, and the results of parametric studies on the effects of die attach on the pull-in behavior of beams of various lengths, widths, and anchor types are presented. An upward shift in pull-in voltage of the studied devices was observed in both simulation and experiment; modelled and measured data were found to correlate closely.     

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

便携式电子产品电路的封装趋势

本文主要描述了便携式电子产品的封装趋势。趋势就是采用芯片级产品电路的MCM封装, 包括SIP和3D封装。这些芯片级产品可以以FC方式或COB方式安装在封装体中。