A reverse-voltage protection circuit for MOSFET power switches

When MOSFET is used as a power switch, it is essential to prevent reverse current flow through the parasitic body diodes under reverse voltage condition. A new built-in reverse voltage protection circuit for MOSFETs has been developed. In this design, an area-efficient circuit is used to automatically select the proper well bias voltage to prevent reverse current under the reverse-voltage condition. This built-in reverse protection circuit has been successfully implemented in a high-side power switch application using a 0.6-μm CMOS process. The die area of the protection circuit is only 2.63% of that of a MOSFET. The latch-up immunity is greater than +12 V and -10 V in voltage triggering mode, and greater than ±500 mA in current triggering mode. The protection circuit is not in series with the MOSFET switch, so that the full output swing and high power efficiency are achieved     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.     

Zero-voltage-switched quasi-resonant buck and flybackconverters-experimental results at 10 MHz

Experimental results are presented for buck and flyback zero-voltage-switched (ZVS) quasi-resonant converters (QRCs) operating above 5 MHz. A design procedure for a buck ZVS QRC is proposed that minimizes voltage stress to the power MOSFET transistor while maintaining zero voltage switching for specified ranges of input voltage and load resistance. A quasi-resonant gate drive scheme is also proposed and implemented in a buck converter. The drive is simple and provides high switching speed. Power dissipation in the gate drive is substantially reduced due to the quasi-resonant operation. The ZVS QRC technique described is suitable for very-high-frequency operation due to its ability to reduce dynamic turn-on losses, Miller effect, dv/dt, and di//dt and can be applied in distributed onboard power supplies     

一种用于数模转换器的电流-电压转换电路

介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

基于CMOS工艺的太赫兹振荡器

在太赫兹频段,无源器件电容电感的品质因数低、电路的寄生参数以及MOS管的截止频率影响使太赫兹振荡器电路难以实现高功率输出。提出一种300 GHz可调谐振荡器,首先,采用改进的交叉耦合双推(Push-Push)振荡器结构,通过输出功率叠加的方法输出二次谐波300 GHz信号,增加了振荡器的输出功率并突破了MOS管截止频率,并通过增加栅极互连电感增加输出功率。其次,太赫兹振荡器摒弃传统片上可变电容调谐的方式,通过调节MOS管衬底电压改变MOS管的栅极寄生电容实现频率调谐,避免太赫兹频段引入低Q值电容,进一步增加了输出功率。提出的太赫兹振荡器采用台积电40 nm CMOS工艺,基波工作频率为154.5 GHz,输出二次谐波为 309.0 GHz,输出功率可达-3.0 dBm,相位噪声为-79.5 dBc/Hz@1 MHz,功耗为28.6 mW,频率调谐范围为303.5~315.4 GHz。     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

一种基于sigma-delta调制的高效率低噪声降压式直流变换器

本论文在提高开关电源效率和降低噪声方面做了一些工作。在效率方面,提出了一个包含死区时间控制,断流模式控制以及栅宽调制功能的高效率功率管驱动电路。在控制回路中采用sigma-delta调制取代传统的PWM调制,降低了开关电源输出中与时钟有关的谐波噪声。本文在 0.35um CMOS工艺条件下实现了一个基于二阶sigma-delta调制的高效率低噪声DC-DC变换器。测试结果表明,此变换器能够达到93%的峰值效率,并且谐波噪声可以比使用PWM调制时低30dB。     

A constant-frequency method for improving light-load efficiency in synchronous buck converters

The low-voltage synchronous rectifier buck topology suffers from low efficiency at light loads due to dissipation that does not scale with load current. In this paper we present a method for improving light-load efficiency in synchronous buck converters by reducing gate drive losses. We propose a new gate drive technique whereby the gate voltage swing dynamically scales with load current such that gate drive loss is traded for conduction loss. Since conduction losses scale with the square of load current, an optimal gate swing exists that, at light loads, is shown to be less than the supply voltage. Using this method we obtain a 6.25% increase in converter efficiency at a load current of 10 mA and operating at a constant switching frequency of 2 MHz.     

A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.     

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction

An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5-/spl mu/m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 /spl mu/s/V for a 1.6-V step-up output change and 13.75 /spl mu/s/V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.     

A novel winding-coupled buck converter for high-frequency, high-step-down DC-DC conversion

This paper analyzes the fundamental limitations of the buck converter for high-frequency, high-step-down dc-dc conversion. Further modification with additional coupled windings in the buck converter yields a novel topology, which significantly improves the efficiency without compromising the transient response. An integrated magnetic structure is proposed for these windings so that the same magnetic cores used in the buck converter can be used here as well. Furthermore, it is easy to implement a lossless clamp circuit to limit the device voltage stress and to recover inductor leakage energy. This new topology is applied for a 12V-to-1.5V/25A voltage regulator module (VRM) design. At a switching frequency of 2MHz, over 80% full-load efficiency is achieved, which is 8% higher than that of the conventional buck converter.     

Low-power analogue computational blocks based on high-performance floating-gate MOSFET resistor

This article proposes a new FGMOS-based programmable FGMOS resistor. A highly linear resistor is implemented by cancelling the non-term present in the drain current equation of MOSFET operating in the linear region. The inherited features of FGMOS resistor are simplicity, programmability, wider bandwidth and very low power dissipation without supply voltage. The power dissipation of the proposed FGMOS resistor is only 985 nW. Analogue computational blocks such as programmable reciprocal circuit, current to voltage converter and low-pass filter as applications of proposed programmable FGMOS resistor are also suggested. The power dissipation of reciprocal circuit and low-pass filter are 14.7 and 131 µW, respectively. To demonstrate the efficacy of the circuits, simulations are carried out using SPICE on 0.13 µm CMOS technology.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

Characterization and comparison of noise generation forquasi-resonant and pulsewidth-modulated converters

A buck converter with a given output filter is operated with pulse-width modulated and quasi-resonant switching schemes at the same nominal load and switching frequency. Electromagnetic interference generated by the natural switching action of the converter is examined by spectral analysis. Interference caused by excitation of parasitic elements is examined experimentally. Quasi-resonant converters are found to have a lower switching frequency harmonic bandwidth than the equivalent pulse-width modulated converter, even with switching frequency control. The most significant parasitic responses are the turn-on current and turn-off voltage of the catch diode and the gate current of the MOSFET. A significant decrease in radiated and conducted noise occurs when the gate drive voltage rise and fall times are increased, which is possible without loss of efficiency using quasi-resonant switching     

A programmable piecewise linear large-signal CMOS amplifier

A high-speed CMOS piecewise linear approximation circuit is presented that can be programmed for correction of nonlinearity after fabrication. The basic building block generates a linear segment, for which slope and position can be adjusted. Adjustments to adapt to arbitrary functions are done with floating gate devices fabricated in standard CMOS technology. The circuit is a voltage-to-current converter with an input range of the full power-supply voltage swing. In an implementation with 18 linear segments less than 0.15% error over rail-to-rail input range was achieved for a linear transfer function. Examples of strongly nonlinear transfer functions approximated to 0.5% accuracy are shown. The large-signal 3-dB frequency is 10 MHz. The implementations are done solely with 2-μm channel length devices     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling     

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.