子系统的动态重构

本文主要讨论了动态重构特性及其发展现状,介绍了利用Ｘｉｌｉｎｘ ＸＣ６２００ ＦＰＧＡ进行系统动态重构的方法。     

The Hypercube as a Dynamically Reconfigurable Processor Mesh

We describe a technique for the efficient processing of large, multidimensional arrays on a MIMD hypercube. The technique allows the hypercube to be used as a processor mesh whose relative dimension sizes may be changeddynamically, while always keeping adjacent array elements on the same node or on physically adjacent nodes. The technique is based on a mapping scheme, calledpermuted Gray code mapping, which is a generalization of the binary reflected Gray code mapping. We also extend the technique to allowinterleavingof the array data over the nodes of the hypercube. This technique can be used to efficiently parallelize scan-line algorithms, including operations such as volume rotation and volume rendering.     

动态重构逻辑及现状

主要介绍动态重构逻辑的概念，发展现状及应用。     

Managing Data-Objects in Dynamically Reconfigurable Caches

The widening gap between processor and memory speeds makes cache an important issue in the computer system design.Compared with work set of programs,cache resource is often rare.Therefore,it is very important for a computer system to use cache efficiently.Toward a dynamically reconfigurable cache proposed recently,DOOC(Data-Object Oriented Cache),this paper proposes a quantitative framework for analyzing the cache requirement of data-objects, which includes cache capacity,block size,associativity and coh...     

基于FPGA的动态可重配置的IP报文过滤系统

IP过滤是把IP数据报文分成不同种类的过程,主要取决于IP报头中的信息.基于软件的字符串匹配已经不能跟上高速的网络传输速度,需要寻找硬件解决方案.这篇论文描述了基于FPGA的动态可重配置内容可寻址存储器CAM(Content Addressable Memorv)在IP过滤中的应用,同时在硬件中采用了Snort入侵监测系统(IDS)的字符串匹配规则.     

基于异构网络处理平台的可配置并行路由查表算法研究

基于通用多核的网络转发性能难以满足高速网络流量线速处理的需求.软硬件结合的异构网络处理平台以其较高的性能和灵活性在网络处理领域得到广泛应用,但是如何基于异构平台实现高效的路由查表算法仍需进行深入研究,多核资源利用率低、共享冲突严重和访存次数多的问题是制约传统路由查表算法在异构网络处理平台实现性能提升的主要问题.为此,基于异构网络处理平台（network processing platform,简称NPP)提出一种可配置并行路由查表机制（configurable parallel lookup,简称CPL).CPL中的多线程并行查找和路由表的多副本存储技术在提高多核资源利用率的同时,实现了零冲突访问路由表项.此外,考虑到不同场景下路由前缀分布的差异,CPL支持通过配置对多级路由表的组织结构进行调整,从而有效地减少了路由表访问次数.最后在NPP上,对CPL和传统的查表算法进行性能测试和对比,验证了CPL的可用性和高效性.     

基于三角形MPU结构的动态重构SoC

SoC是嵌入式系统应用开发的高端代表。SoC的研究主要在设计和结构方面展开,其中SoC的重构是一个热点,而动态重构则是新的研究领域。本文提出了一种多MPU核的SoC动态重构的概念-基于三角形MPU结构的动态重构SoC。三角形结构是一种稳定结构,基于三角形的MPU形成监、运、备三个支撑点,构造了SoC动态重构的稳定结构。文中还阐述了一种三角形MPU结构SoC的动态重构方案。     

Low Power Encoding Techniques for Dynamically Reconfigurable Hardware

In this paper, an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to automatically minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 41%.     

基于FPGA的动态可重配置的IP报文过滤系统

IP过滤是把IP数据报文分成不同种类的过程,主要取决于IP报头中的信息。基于软件的字符串匹配已经不能跟上高速的网络传输速度,需要寻找硬件解决方案。这篇论文描述了基于FPGA的动态可重配置内容可寻址存储器CAM(ContentAddressableMemory)在IP过滤中的应用,同时在硬件中采用了Snort入侵监测系统(IDS)的字符串匹配规则。     

可重构异构系统结构研究

可重构异构系统是由通用微处理器、可重构模块、专用ASIC、IO接口等资源构成的异构并行处理系统,文中提出的可重构异构系统结构融合了不同的计算资源,使系统中的某些资源能够很大限度地满足某种应用的模式和处理要求.系统中可重构模块的硬件功能可以通过在线重构技术加以改变,各模块之间的互连关系可通过重构互连控制器调节和仲裁.这种可变性使计算系统能适应更大范围的应用需求,向一体化和高性能的方向发展.     

动态可重配置的星上嵌入式实时计算系统

卫星上由于特殊条件的限制,计算机处理速度满足不了对信号处理的需要,而且不能在有限的硬件规模和功耗的情况下灵活地实现各种计算处理功能。提出了一种基于嵌入式微处理器配合大规模现场可编程门阵列（FPGA）的动态可重配置结构的星上实时计算系统的体系结构设计,可在一块FPGA资源上通过动态重配置实现不同的信号处理功能。实际应用证明,处理速度和性能得到了大幅度提高。     

The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling

Although most current multicore processors are homogeneous, microarchitects are now proposing heterogeneous core implementations, including systems in which heterogeneity is introduced at runtime. This article shows that operating system schedulers must consider dynamic heterogeneity or suffer significant power-efficiency and performance losses.     

Micro-Task Processing in Heterogeneous Reconfigurable Systems

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.     

一种动态可重构Reed-Solomon译码器的设计

针对RS译码器结构复杂,资源消耗大的问题.提出了一种基于动态可重构技术的RS译码器;该译码器将伴随多项式计算和钱氏搜索算法在同一个可重构模块RSCM中通过动态改变电路结构,以时分复用的方式实现;给出了基于状态机的译码控制器,实现各功能模块的调用;采用VHDL语言实现,在Quartus Ⅱ 7.2环境下进行仿真;结果表明,该译码器能有效降低硬件资源占用率,最高时钟频率达到124MHz.     

可动态重构的旋翼飞行器设计与运动特性分析

针对旋翼飞行器因机体结构受运动路径中空间变窄限制而无法连续穿越的问题,研究设计了一种可动态重构的旋翼飞行器,通过改变机体构形实现对空间变化的运动应对,提高飞行器在复杂环境下连续运动作业的能力.该系统采用链式模块化结构,通过旋转关节实现构形的2维变化.根据机体结构特点和运动控制方式,基于D-H(Denavit-Hartenberg)规则推导了空间变换矩阵,求解了变化重心,建立了机体运动学模型.基于几何、动力和控制响应约束,提出了构形变换的求解方法,并针对该模型给出了边界条件.最后进行了飞行器稳定性、操纵性及临界构形实验.结果 表明,构形变换过程中,飞行器姿态稳定,无明显突变,各轴向最大变化量在4°以内;濒近临界构形时飞行器操控顺畅,跟踪控制响应能够在0.1s内完成.实验验证了姿态可控的临界构形角度集为{180°,180°,113°},通过几何运算,采用固定航向方式,飞行器的通过半径可缩小21.89％,结合航向控制的方式,最大通过半径可缩小67％.飞行器具备稳健完成动态重构和通过窄间隙的能力.     

基于中间件的动态重配置容错对象管理框架

该文从容错QoS角度出发,为现有的基于中间件的容错对象管理框架增加自适应特性．首先把动态童配置定义成容错属性集（及其实现）、计算环境和资源变化描述、动态调整算法三者之间的互动关系,然后采用反射模型和发布／订阅模型建立了一个动态重配置管理框架,可以使系统在发现计算环境的变化、定制动态调整算法等多方面得到有力的支持,为系统有效实施动态重配置奠定了基础．     

Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses

A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an arbitrary number of synaptic connections, each with tunable conductance and reversal potential. The array of silicon neurons functions as an address-event (AE) transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven digital bus. Address encoding and conflict resolution of spiking events are implemented via a randomized arbitration scheme that ensures balanced servicing of event requests across the array. Routing of events is implemented externally using dynamically programmable random-access memory that stores a postsynaptic address, the conductance, and the reversal potential of each synaptic connection. Here, we describe the silicon neuron circuits, present experimental data characterizing the 3 mm times 3 mm chip fabricated in 0.5-mum complementary metal-oxide-semiconductor (CMOS) technology, and demonstrate its utility by configuring the hardware to emulate a model of attractor dynamics and waves of neural activity during sleep in rat hippocampus     

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units

A partitioning methodology between the reconfigurable hardware blocks of different granularity, which are embedded in a generic heterogeneous architecture, is presented. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by a 2-Dimensional Array of Processing Elements. Critical parts, called kernels, are mapped on the coarse-grain reconfigurable logic for improving performance. The partitioning method is mainly composed by three steps: the analysis of the input code, the mapping onto the Coarse-Grain Reconfigurable Array and the mapping onto the FPGA. The partitioning flow is implemented by a prototype software framework. Analytical partitioning experiments, using five real-world applications, show that the execution time speedup relative to an all-FPGA solution ranges from 1.4 to 5.0.     

面向异质结构的可重构任务在线布局算法

基于同质结构模型的可重构任务布局算法和内部资源多样的可重构器件不相适应,不利于实际运用.针对BlockRAM等静态单元在器件上的分布对硬件任务存在位置约束的问题,建立了异质结构的器件和硬件任务模型,并提出一种基于相对任务覆盖度的在线布局算法.通过为布局任务等待队列设立滑动窗口,根据窗内任务集合对器件空闲单元的相对任务覆盖度选择当前任务的放置位置,兼顾后续任务的布局需求,从而提高了整体布局效率.实验结果表明,该算法能取得较低的任务平均等待时间和较高的器件利用率,优于First Fit算法.     

基于SOPC的可穿戴计算机动态重构模块设计与实现

针对可穿戴计算机任务的多变性及多样性,研究通过动态重构技术和SOPC设计方法两者相结合来制造适合可穿戴计算机的动态重构方式,同时对基于SOPC的可穿戴计算机动态重构模块进行了设计与实现．．