N-channel enhancement-mode MOSFET characteristics from 10 to 300 K

Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have not been previously reported, it has not been established whether conventional models can be applied for MOSFET circuit design at 77 K. We present here the temperature dependence of a full set of MOSFET circuit model parameters for channel lengths from 2.5 to 8.5 µm and for temperatures ranging from 10 to 300 K. Temperatures below 77 K are of interest in evaluating effects of impurity freezeout and temperatures above 77 K are important since actual device temperatures will be above the ambient. Overall, we find that the mobility and the threshold voltage are the dominant temperature dependent parameters and that conventional I-V characteristics persist down to 77 K. Below 77 K, some new features appear in the I-V characteristics. However, the conventional behavior down to 77 K suggests that standard (circuit models can be used for circuits operating at 77 K. Such circuits would be about four times faster than at room temperature and, with liquid nitrogen cooling, would provide an order of magnitude higher power density for VLSI.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

Studies on an In0.53Ga0.47As/In0.52Al0.48As single-quantum-well quasi-MISFET

We describe here the properties of a novel InGaAs/ InAlAs quasi-MISFET in which an inverted modulation-doped single quantum well forms the channel and an undoped semi-insulating InAlAs constitutes the gate barrier. The entire structure is grown lattice-matched to InP continuously by molecular-beam epitaxy in a single step. Rapid thermal annealing of implanted semiconductors and ohmic contacts have been investigated and have been used successfully in the fabrication of the MISFET's. Improved performance is obtained with the incorporation of Ti in the source-drain metallization, with which contact resistances as low as 0.1 ω . mm are measured. Charge-control modeling of the proposed device predicts the carrier concentration in the channel region fairly well at room temperature. A quantum mechanical modeling of the device in the effective mass approximation also has been done. The thickness of the InAlAs doping layer is found to be an important parameter that controls the device turn-on characteristics. The velocity-field characteristics of the two-dimensional channel electrons were measured by pulse current-voltage and pulsed Hall techniques. The maximum velocities measured at 300 and 77 K are 1.5 × 10⁷and 1.7 × 10⁷cm/s, respectively. Fairly high electron mobilities are measured in single-quantum-well MISFET structures even with well thicknesses as small as 100 Å. The InAlAs gate barrier is effective in reducing the gate leakage current. Gate leakage currents are reduced further with a composite dielectric consisting of oxidized Al and InAlAs. An extrinsic transconductance of 310 mS/mm is measured in a 1.0-µm gate device at 300 K. A value of fT= 32 GHz, measured in a 1.0-µm device, is the best obtained so far with this material system. It is expected that submicrometer gate lengths will lead to even better performance.     

High-accuracy physical modeling of submicrometer MOSFET's

When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.     

New infrared detector on a silicon chip

We report a single-crystal Si-Ge structure which works as an efficient photodetector in the wavelength region of up to 1.5 µm. The multilevel structure is grown by molecular-beam epitaxy on an n-type 3-in silicon substrate and consists of the following layers: n⁺silicon (1000 Å), n⁺GexSi1 - xalloy (1800 Å, graded in ten steps fromx = 0tox = 1), n⁺germanium (1.25 µm), undoped germanium (2.0 µm), and p⁺germanium (2500 Å). Top three layers form a germanium p-i-n diode, which is removed from the Ge-Si interface by a buffer layer of high conductivity. An advantage of this structure is that its performance is insensitive to material defects in the buffer layers. Moreover, transmission electron microscopy shows that the density of dislocations introduced by lattice mismatch at the Ge-Si interface falls off with the separation from the interface. Our first experimental structures do exhibit the characteristics of a germanium p-i-n diode. The spectral response curves agree with those given in the literature for germanium, both at room and liquid nitrogen temperatures. For the incident light wavelength of 1.45 µm we have measured a quantum efficiency of 41 percent at T = 300 K. we believe that our approach opens an attractive possibility of fabricating complete infrared optoelectronic systems on a silicon chip.     

Polycrystalline silicon thin-film transistors on a novel 800°C glass substrate

A new polycrystalline silicon thin-film transistor (TFT) technology using a potentially low-cost glass substrate is reported. Transistors are made using modified conventional n-channel MOS processes at temperatures of 800°C or less, with a final hydrogen implantation step. These transistors show leakage currents of 2 × 10^-11A/µm of channel width, ON-to-OFF current ratios of 1 × 10⁴at Vds= 9.0 V, and good dc stability. This combination of polycrystalline silicon transistors on potentially low-cost glass substrates offers a new option in the choice of active device technology for large-area flat-panel liquid crystal displays (LCD's).     

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = tpdPd) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, CL= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness Xo= 450 Å with VDD= 3.0 V, to yield tpd= 400 ps and Pd= 250 µW (tpdPd= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for tpdand Pd. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for tpddescribes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.     

Effects of grain boundaries on laser crystallized poly-Si MOSFET's

Data are reported for n-MOSFET's fabricated in laser crystallized poly-Si on amorphous insulating substrates. The dependence of electrical characteristics on the effective channel length in the range of 100 to 0.3 µm and on channel width from 120 to 20 µm is presented. The electron surface mobility is found to increase as the channel length is reduced, approaching that of devices in single-crystalline silicon. The source-to-drain leakage current, negligible for long channels, rapidly increases for channels shorter than ≃ 3 µm. This excessive current results from grain boundary diffusion of As from source and drain during high temperature fabrication steps.     

A novel EPROM device fabricated using focused boron ion-beam implantation

A novel floating-gate avalanche injection (FAMOS) type erasable programmable read-only memory (EPROM) device is demonstrated, with a heavily focused ion-beam (FIB) implanted region of about 0.2-µm width at the drain edge of the channel. This heavily B⁺- doped region permits a higher electric field near the drain edge, resulting in a remarkable increase of the hot-carrier generation rate, and reduces both the programming voltage and programming time. A three-dimensional device simulator, CADDETH, predicted that the electric field at the drain edge would increase by about six times, which would lead to hot-carrier generation efficiency three orders of magnitude higher. The programming voltage of a fabricated device is reduced by about half, in obtaining the same programming characteristics as the conventional device. The programming time of a fabricated device with an effective channel width of 3.1 µm is 50 ms, which is 1 /50 of that of a conventional device.     

Experimental results on submicron-size p-channel MOSFET's

We report results on p-channel MOSFET's with channel lengths as small as 0.5 µm. Using design criteria obtained from numerical simulation, the devices have been fabricated by a low temperature process with very short annealing times. Fabricated devices with submicron channel lengths are dominated by velocity saturation of holes. Comparing the drive capability of n- and p-channel devices, we find the intrinsic device currents to be within a factor of 1.4 for a channel length of 0.5 µm.     

A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

Single electron switching events in nanometer-scale Si MOSFET's

High-resolution ac measurements of drain conductance at low temperatures have been made on silicon MOSFET's with channels as narrow as 0.1 µm. These devices show discrete switching events in the channel resistance associated with individual electrons being captured and emitted from single interface traps. The voltage and temperature dependence of this switching gives detailed information on the characteristics of the trap and its distance from the interface. This switching is a component of low-frequency noise in MOSFET's and may be an important limit to the performance of small transistors.     

Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Free electron laser annealing of silocon carbibe

We have applied a free electron laser (FEL) to crystallize amorphous silicon carbide (a-SiC) and to remove the damage and activate the dopant of a damaged layer of nitrogen implanted cubic silicon carbide (3C-SiC) films at room temperature. The FEL has two main characteristics, wavelength tunability and ultrashort-pulse operation (~10 ps) with intense peak power (~MW). The wave-length was selected at the energy of the Si-C stretch mode in order to excite the lattice vibration directly. We observed the crystallization of a-SiC occurs at room temperature when irradiation with a 12.6 μm FEL. The present results indicate that FEL annealing (12.6 μm: transverse optical mode, 10.3 μm: longitudinal optical mode) is effective for recrystallization and activation of an ion-implanted SiC films.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

New technology towards GaAs LSI/VLSI for computer applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

Scaling issues related to high field phenomena in submicrometer MOSFET's

Both enhancement and depletion n-channel MOS devices with electrical channel lengths between 1 and 0.3 µm are characterized in terms of carrier heating effects. The effect of gate oxide thickness on the two-dimensional (2-D) electric field distribution has been analyzed through 2-D numerical device simulation, and its impact on carrier heating process has been experimentally quantified. Our results allow some conclusions for reduced supply voltages (2 and 3 V for temperatures of 77 and 300 K, respectively) for future NMOS technologies with design rules of 0.75 µm.     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

Switching characteristics of scaled CMOS circuits at 77 K

Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 µm, Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations.