Runtime Support for Multicore Packet Processing Systems

Network processors promise a flexible, programmable packet processing infrastructure for network systems. To make full use of the capabilities of network processors, it is imperative to provide the ability to dynamically adapt to changing traffic patterns in the form of a network processor runtime system. The differences from existing operating systems and the main challenges lie in the multiprocessor nature of NPs, their on-chip resource constraints, and real-time processing requirements. In this article we explore the key design trade-offs that need to be considered when designing a network processor operating system. In particular, we explore the performance impact of application analysis on partitioning, traffic characterization, workload mapping, and runtime adaptation. We present and discuss qualitative and quantitative results in the context of a particular application analysis and mapping framework. The observations and conclusions are generally applicable to any runtime environment for network processors.     

Real-Time Adaptive Background Modeling for Multicore Embedded Systems

Current trends in microprocessor design integrate several autonomous processing cores onto the same die. These multicore architectures are particularly well-suited for computer vision applications, where it is typical to perform the same set of operations repeatedly over large datasets. These memory- and computation-intensive applications can reap tremendous performance and accuracy benefits from concurrent execution on multi-core processors. However, cost-sensitive embedded platforms place real-time performance and efficiency demands on techniques to accomplish this task. Furthermore, parallelization and partitioning techniques that allow the application to fully leverage the processing capabilities of each computing core are required for multi-core embedded vision systems. In this paper, we evaluate background modeling techniques on a multicore embedded platform, since this process dominates the execution and storage costs of common video analysis workloads. We introduce a new adaptive backgrounding technique, multimodal mean, which balances accuracy, performance, and efficiency to meet embedded system requirements. Our evaluation compares several pixel-level background modeling techniques in terms of their computation and storage requirements, and functional accuracy for three representative video sequences, across a range of processing and parallelization configurations. We show that the multimodal mean algorithm delivers comparable accuracy of the best alternative (Mixture of Gaussians) with a 3.4× improvement in execution time and a 50% reduction in required storage for optimal block processing on each core. In our analysis of several processing and parallelization configurations, we show how this algorithm can be optimized for embedded multicore performance, resulting in a 25% performance improvement over the baseline processing method.     

嵌入式系统编程中的代码优化

本文从嵌入式系统的特点出发,阐述了嵌入式系统编程语言的选择以及代码优化的方法.首先分析嵌入式系统特点和嵌入式系统编程的要求,在此基础上阐述了嵌入式实时程序设计中语言的选择,接着结合嵌入式软件开发的实践,着重阐述嵌入式软件开发中代码优化方法.最后做出总结,提出综合利用各种方法的必要性.     

Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization

Journal of Signal Processing Systems -     

DSP环境下C语言编程的优化实现

重点讨论了用C语言进行DSP软件设计时的一些常用的编程优化策略，旨在实现代码的高效和运算速度的提高。详细阐述了这些优化策略的特点、应用规则和性能分析。这些策略同样适用于C^ 开发环境。同时给出了程序设计实例。     

向集成微控制器/DSP内核发展的趋势采用集成DSP与微处理器内核的嵌入式应用

嵌入式应用包括信号处理算法与控制算法,在多种实时嵌入式系统中,这两种算法共同执行必需的功能,因此我们应了解控制算法与数字信号处理器(DSP)算法是如何实现互操作性的.     

Message-Passing Programming for Embedded Multicore Signal-Processing Platforms

Recently, embedded multicore platforms have become popular for signal processing, but software development for such platforms is still very slow. First, parallel programming is more challenging than sequential programming to average programmers. To make the problem worse, software is not portable among the platforms, since each multicore signal-processing platform offers its own programming interface/language. We believe this problem can be relieved by adding the support of a standard message-passing programming to embedded multicore platforms. In particular, we would like to leverage MPI, the most successful message-passing system, which practically enables the development of portable applications to run on many parallel machines. There are technical challenges to support MPI on embedded multicore platforms: the size of the library, architecture issues, and performance issues. This paper identifies and addresses these issues. To enable the reuse of existing MPI programs and make message-passing programming portable and efficient, we designed a light-weight MPI-like message-passing library with a three-layer modular design, where the top two layers are mostly platform-independent, and the bottom layer enables platform-specific optimizations. This approach has allowed us to effectively support message-passing on several popular embedded multicore signal-processing platforms, including the IBM CELL and the ITRI PAC Duo. Our results show that message-passing programming is a viable solution for multicore signal processing applications and may be considered by platform vendors.     

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.     

嵌入式操作系统管理汇聚应用

当今许多复杂的嵌入式系统要求信号处理和信号控制两种功能.过去这两种功能一直属于DSP和微控制器(MCU)两种独立的器件.然而,汇聚处理器的推出改变了这种现状,将DSP和MCU两种功能集成到一种灵活体系结构中,典型的代表有ADI公司的B1ackfin处理器系列.     

A Framework for Data Partitioning for C++ Data-Intensive Applications

We present an automated framework that partitions the code and data types for the needs of data management in an object-oriented source code. The goal is to identify the crucial data types from data management perspective and separate these from the rest of the code. In this way, the design complexity is reduced allowing the designer to easily focus on the important parts of the code to perform further refinements and optimizations. To achieve this, static and dynamic analysis is performed on the initial C++ specification code. Based on the analysis results, the data types of the application are characterized as crucial or non-crucial. Continuing, the initial code is rewritten automatically in such a way that the crucial data types and the code portions that manipulate them are separated from the rest of the code. Experiments on well-known multimedia and telecom applications demonstrate the correctness of the performed automated analysis and code rewriting as well as the applicability of the introduced framework in terms of execution time and memory requirements. Comparisons with Rational’s Quantify^TM suite show the failure of Quantify^TM to analyze correctly the initial code for the needs of data management.     

嵌入式操作系统Visual DSP++Kernel的原理与应用

本文剖析了ADSP中基于嵌入式操作系统VisualDSP++Kemel(VDK)开发工具的原理与应用、优点、常用库函数、DEBUG工具以及它的具体应用.通过对VDK的学习,可以使学生进一步理解和掌握嵌入式操作系统的工作原理,提高他们的应用和开发能力.     

浅谈心理学在C++程序设计教学中的应用

针对C＋＋程序设计教学的困难,本文结合为大学新生授课的实践经验,以学习动机理论、学习迁移理论、感知规律的应用为例,探讨心理学对于提高C＋＋程序设计教学效果的积极作用。     

基于TI C6000系列DSP的C／C＋＋程序优化技术

在现代DSP的开发中,越来越多地采用C/C++作为开发语言,而C/C++程序的优化成为DSP软件开发的重要环节.在此介绍TI C6000的软件开发流程,重点讨论C6000系列的C/C++程序优化技术,包括优化流程,C/C++代码优化方法,编写线形汇编代码优化方法等.为DSP的C/C++软件开发提供了全面的程序优化技术和方法,对实际系统的开发具有重要的现实意义.     

面向嵌入式系统的I2C总线设计和测试

I^2C是一种中低数据速率主／从通信总线。物理层是一种简单的信号交换协议,该协议基于总线设备以及用于驱动或释放总线线路设备之上的集电极开路输出。简单的硬件设计和较低的数据速率使得所有的工程师都能利用I^2C作为一种通信解决方案。     

DSP环境下C代码的手工汇编优化

由于DSP器件的特殊结构,使得该平台上C编译器的效率较低,编译生成的汇编代码含有大量冗余,无法充分发挥DSP强大的运算能力,因而对C语言程序进行手工汇编优化就成为DSP软件开发和移植中常用的方法。TMS320C5410是TI推出的一款16位定点DSP芯片,结合在该芯片上优化实现G.729语音编码压缩算法的经验,详细探讨了手工汇编优化过程中使用的优化策略以及其他注意事项。     

嵌入式产品在GPS监控系统中的应用

1 GPS监控系统介绍 GPS车辆调度系统的建设,首先要考虑监控覆盖范围、实时性、调度业务、车辆容量、刷新速率等要求来选择合适的无线数据链路和电子地图,以及开发相应业务软件满足用户的要求。就目前GPS车辆调度系统而言,无线数据链路应用较多的为GSM通信方式,这主要由于其覆盖范围广、无需架设基站、可实现语音/短信等功能的优点所决定的。 1.1 车载终端 车载终端设备包括控制单元、显示单元(可选)、GPS、GPS天线、GSM手机(或其他通信模块)和防盗报警器等。主要功能有防盗报警、导航和通话。 1.2 无线数据链路 无线数据传输设备…     

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

A heterogeneous multicore system-on-chip (SoC) has been developed for high-definition (HD) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for cipher and high-resolution video decoding; one general-purpose accelerator (MX); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a package), through DDR2 SDRAMs and a flash memory that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in a 90 nm generic CMOS technology.      

嵌入式逻辑分析技术及其在FPGA系统开发中的应用

介绍了嵌入式逻辑分析仪,特别是SignalTapⅡ的功能和特点。利用Chip EditorViews、Technology Map Viewer等工具,简要分析了SignalTapⅡ的内部结构和工作原理。结合实例,说明了如何使用SignalTapⅡ调试基于FPGA的数字系统。     

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes coarse-grained reconfigurable logic with a microprocessor. The reconfigurable hardware is a 2-D array of processing elements connected with a mesh-like network. Analytical results derived from mapping seven real-life digital signal processing applications, with the aid of an automated design flow, on six different instances of the system architecture are presented. Significant overall application speedups relative to an all-software solution, ranging from 1.81 to 3.99 are reported being close to theoretical speedup bounds. Additionally, the energy savings range from 43% to 71%. Finally, a comparison with a system coupling a microprocessor with a very long instruction word core shows that the microprocessor/coarse-grained reconfigurable array platform is more efficient in terms of performance and energy consumption.