A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

基于二分法的混合信号接口板的设计

介绍了一种基于二分算法的混合信号接口板.该接口板可通过编程任意配置测试芯片管脚实现模拟或数字信号输入端口与输出端口的无损连接,可广泛应用于芯片自动化测试领域.本设计采用二分法来实现管脚的分级,采用遍历引脚逐一比较的方式来配置引脚连接,通过控制模拟开关阵列来实现模拟信号的输入与输出端口连接,通过FPGA实现数字信号的输入与输出端口连接.该设计方案利用极少的开关实现了复杂线路的配置,具有较高的资源利用率,极大降低了芯片测试的难度和成本.     

基于CPLD的线阵CCD信号采集系统设计

文中基于复杂可编程逻辑器件设计一款高分辨率的线阵CCD信号采集系统。利用Verilog硬件描述语言进行了CPLD控制模块以及逻辑单元的程序设计,由图像专用A/D芯片中的相关双采样等特殊功能,实现了对CCD输出信号的噪声处理和模数转换,通过USB2.0接口实现了计算机终端采集和控制指令的实时传输。采用CPLD的设计方法具有驱动时序精确、采样速率快、抗干扰性强和输出信号稳定等特点。仿真结果证明,系统总体性能较好,上位机能正确显示采集到的CCD数据,噪声在允许的范围内,在不同的工作环境下,系统性能稳定。     

面向音频应用的可配置片上系统的设计与实现

基于一款通用的16位定点数字信号处理器,结合D/A转换器、A/D转换器和放大器等模拟电路模块,设计并实现了一种面向音频应用的可配置片上系统.该系统支持立体声输入输出,具有8～48 kHz之间可编程的采样频率,以及可编程的输入输出放大器增益.同时,设计使用了24位高精度Σ-Δ A/D转换器,并配有可供选择的数字滤波器.为支持不同应用,系统提供24位或16位的可编程字长调节.系统芯片工作在1.8 V电压下,芯片内各部分支持挂起或睡眠状态,有利于低功耗的便携式应用开发.介绍了部分关键功能模块的仿真、验证和测试,以及整个系统仿真模型的建立.     

Programmable digital vehicle control system

The programmable digital vehicle control system or PDVCS is based upon the Intel 8080A microprocessor and is designed to replace the hardwired discrete components traditionally used in the on-board control of automated rapid transit vehicles. Although designed specifically for the advanced group rapid transit (AGRT) system under development by the Boeing Company, with funding by the Department of Transportation, the PDVCS can easily be adapted for use in any automated transit system. A breadboard PDVCS has been programmed to perform the basic AGRT longitudinal control system functions, including closed-loop emergency braking, and has been subjected to closed-loop laboratory testing. Prototype tachometers and a seventh-order nonlinear analog computer simulation of motor, brake, and vehicle dynamics were used to close the control loop for test purposes; command scenarios were input manually. The test results demonstrate the feasibility of microcomputers in on-board vehicle control and show their capability to meet the performance requirements associated with a short headway (3 s) system.     

An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling

A single-chip multiple-channel D/A converter is described. The NMOS chip contains a combination of digital and analog functions. Eight output channels with 8 bit accuracy are provided and each channel has programmable end points. The values for the data and the end points are stored in an internal RAM. Sample and-hold functions are completely on-chip. Only one multiplexed opamp is required for the analog functions. The entire control logic is incorporated in an easily testable PLA. The active chip area is 8 mm/SUP 2/. There are three power supplies (15,5,-5) with a total power dissipation of 120 mW. Updating of the eight channels occurs at a 16 kHz rate (5 MHz clock). The circuit aims at applications in microprocessor driven control systems in the industrial and consumer products field.     

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.     

基于DDS频率源的设计与实现

介绍了DDS的基本工作原理,阐述了DDS技术局限性,最终实现了一种基于FPGA+DDS 可编程低相位噪声的频率源,输出信号范围170～228 MHz。测试结果表明,该频率源具有高频率分辨率和低相位噪声等特点,能够满足通信系统对频率源的设计要求。     

A Wide-Tracking Range Clock and Data Recovery Circuit

A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER <10^-12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.     

现场可编程模拟阵列的微处理器配置模式及接口方法

现场可编程模拟阵列AN10E40加上直观性软件AnadigmDesigner,给数字和模拟电路设计者提供了设计模拟电路的便利条件,可以在AN10E40上快速设计精确、无漂移、具有温度补偿及可编程的模拟电路.AN10E40有两种装载配置SRAM的工作模式:模式0是微处理器引导模式,模式1是串行ROM引导模式.文中介绍了现场可编程模拟阵列AN10E40的微处理器配置模式,给出了AN10E40与51系列单片机的接口方法及程序设计.     

一种∑-Δ模数转换器

∑-Δ模数转换器是一种高度集成化的新型模数转换器,采用过采样技术,无需采样保持电路.它内置了多路复用器、可编程放大器、调制器、数字滤波器、校准系统和串行接口.其转换率最高为150kHz,分辨率可达24位.本文对该系列∑-Δ模数转换器的原理结构及其操作进行简单介绍.     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

Testing of programmable analog neural network chips

Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by National Science Foundation under Grant MIP-8904172.     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

Adaptive Narrowband Interference Suppression in Multiband OFDM Receivers

The analysis and optimization of a notch filter to combat in-band narrowband interference (NBI) for multiband orthogonal frequency division multiplexing (MB-OFDM)-based ultra-wideband (UWB) systems is presented. Unintentional radiation of electronic devices can reside in the UWB band and jam the communication. Erasing the interference with a programmable analog notch filter reduces the requirement for the analog-to-digital converter resolution in the presence of NBI. The order and approximation of the notch filter are determined, and the filter’s bandwidth is optimized to minimize the packet error rate. Simulation results indicate that the UWB system with suppression scheme can handle up to 14 dB more in-band interference power.     

毫米波大规模MIMO系统中基于智能搜索的混合预编码算法

为解决传统全连接结构毫米波大规模MIMO系统高硬件成本和实现难度大的问题,本文提出了一种基于智能搜索的部分连接结构混合预编码算法。该算法在基站端采用经典的迫零数字预编码,在模拟预编码部分单独设计模拟预编码矩阵,避免了数字、模拟预编码矩阵联合设计的高复杂度,并利用模拟预编码矩阵的块对角化特性,将其设计问题转化为最优化问题,采用SBO（satin bowerbird optimization）优化算法解决此问题。针对原始SBO算法易陷入局部最优的缺点,提出了一种基于动态突变概率的DSBO（satin bowerbird optimization based on dynamic mutation probability）算法。针对移相器分辨率有限的情况,改进了DSBO算法,使之能解决此离散优化问题。仿真结果表明,与其他现有算法相比,提出的算法具有更高的系统容量和更低的误码率,且能处理移相器分辨率有限的情况。      

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

Subscriber Line Testing for Digital Switching Offices

This paper presents an overview of subscriber line testing as provided in Northern Telecom's Digital World^®family of host and remote digital switching systems. Capabilities provided in Digital World satisfy the major telco needs related to subscriber line testing. The various products incorporate interfaces to external test systems as well as internal line test facilities. A new subscriber line measurement technique is identified. It offers further advantages in speed and accuracy and has many potential applications in the analog and digital switching environments.     

A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSPusing partial response signaling with maximum likelihood detection

A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper. PR-IV (minimum signal bandwidth) for signal encoding is used, along with ML (maximum likelihood) detection to achieve superior error rate performance. Signal equalization is provided using a programmable ten-tap FIR (finite impulse response) digital filter. This read/write channel is implemented on a single chip using analog circuits and 20 K CMOS logic gates. The 7.5 mm square chip uses a 5 V, 1 μm, BiCMOS process with a 6 GHz n-p-n and a 1 GHz p-n-p and is packaged in a 100-lead metal QFPK (quad flat pack)