An analytical quasi-saturation model considering heat flow for aDMOS device

This paper reports an analytical quasi-saturation model considering heat flow for a DMOS device. As verified by the PISCES results, the analytical model, which considers heat flow provides a good prediction of the much worse quasi-saturation behavior due to the elevated lattice temperature. This is a result of the limited heat sinking capability of the thermal contact node. Based on the analysis, for a DMOS device operating with a contact thermal resistance of less than 10⁴ K/W, the drain current at quasi-saturation is found acceptable with a lattice temperature below 350 K     

Noise behavior of a static induction transistor between 77 K and 300 K

The noise behavior of a Static Induction Transistor (SIT) has been studied. The SIT transistor has a relative high noise level for the low and middle frequency range and it increases with decreasing temperature. Spectral analysis for different temperatures has been carried out. Observation of the noise spectra indicates generation-recombination noise from a single energy level trap. An activation energy of 0.13 eV has been measured which might originate from a previously observed SiO complex in the bulk, this may be an important noise source in the SIT.     

Hot-electron-induced photon energies in n-channel MOSFETs operatingat 77 and 300 K

A detailed experimental study of the spectral distribution of hot-electron-induced photon emission in n-channel MOSFETs is presented. The study significantly improves on previous work by considering energies up to 3.1 eV and different operating temperatures. It is shown that in contrast with previous results, the photon energy distribution is markedly non-Maxwellian, thus suggesting that the same is true for the energy distribution of the channel electrons     

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 μm     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V_B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V_B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field     

Frequency limits of GaAs and InP field-effect transistors at 300 K and 77 K with typical active-layer doping

InP FET's with active layer doping of 10¹⁷donors/ cm³have limiting values of fTroughly fifty per cent higher than those of equivalent GaAs devices for lengths ranging from 0.5 µm to 3 µm at 300 K, and from eighty percent to forty percent higher in this gate length range at 77 K.     

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 μm L_eff, self-aligned TiSi₂ double-level metal, and an average minimum feature size of 1.35 μm. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed     

MOSFET behavior and circuit considerations for analog applications at 77 K

We present an investigation into the behavior of silicon MOS transistors and analog circuits operated at liquid-nitrogen temperature (LNT). Simple scaling rules are used to predict the LNT performance of CMOS operational amplifier circuits designed for room-temperature operation. Measurements show that unity gain frequency and slew rate can be improved by the same amount as the mobility increase with no loss of stability if bias currents are properly controlled. We also show that room-temperature CMOS amplifier circuits can be redesigned for 77-K operation by reducing channel widths and compensation capacitor area, giving performance equal in most respects to that of unscaled circuits at room temperature. However, 1/f noise is degraded by such redesign. Similar considerations of NMOS amplifiers show that such circuits do not benefit greatly from operation at liquid-nitrogen temperature. To aid in studying the temperature dependence of the sheet resistance of diffused resistors, a computer program was developed based on available models for bulk mobility and carrier freeze-out. Accurate predictions require a temperature dependence for lattice scattering that differs from previously reported values.     

Proton-bombardment formation of stripe-geometry heterostructure lasers for 300 K CW operation

A method of defining the active region of stripe-geometry junction lasers by proton-bombardment-induced high-resistivity layers is described. The method yields more reproducible mode patterns and lower threshold currents than the previously used oxide insulation. The improved lasers operated continuously at heat-sink temperatures up to 110°C.     

A fully analytical AC large-signal model of the GaAs MESFET fornonlinear network analysis and design

A fully analytical version of an AC large-signal model for the GaAs MESFET is presented. The source model is based on basic principles and the actual physics and geometry of the device. The analytical version was developed by curve fitting the analytical expressions to the source model. The accuracy of the model for microwave circuits is demonstrated using simulation examples of a power amplifier and a mixer     

Analysis of channel noise and threshold voltage in sos-MOS transistors in the temperature range of 77–300 K

A characterization is carried out for MOS transistors on sapphire on the basis of an analysis of the threshold voltage V_T and the channel noise current using the doping of the silicon (2 × 10¹⁵ cm^?3 to 6 × 10¹⁶ cm^?3) and the temperature (77–300 K) as parameters.The experimental values of V_T, as a function of the bulk potential V_BS, show that it is possible to deplete the silicon film fully for doping magnitudes less than 10¹⁶ cm^?3. The modelling of V_T vs. V_BS, using a relation derived for bulk Silicon devices, points to finite volume effects of the silicon.The analysis of the noise shows, at 300 K, an excess noise which follows a 1/f law for the Silicon film not fully depleted and a 1/f² law in the depleted case. On the other hand, at 77 K, this noise always shows a 1/f behaviour. The study of the noise as a function of temperature suggests that the traps of the Silicon-Sapphire interface become more active around room temperature than around 77 K. The thermal level is reached at about 1 MHz at room temperature for all devices, whereas at 77 K it is only observed for the higher doping devices.     

A closed-form analytical forward transit time model consideringspecific models for bandgap-narrowing effects andconcentration-dependent diffusion coefficients for BJT devices operatingat 77 K

The authors report a closed-form analytical low-temperature forward transit time model considering bandgap-narrowing effects and concentration-dependent diffusion coefficients based on the entire shape of the emitter and base doping profiles for bipolar junction transistor (BJT) devices operating at 77 K. As verified by the PISCES simulation results, the new closed-form analytical model provides a better low-temperature forward transit time model compared to the model in which bandgap-narrowing effects and concentration-dependent diffusion coefficients are not considered     

Estimation of drift mobility in InGaAsP semiconducting alloys from photoluminescence at 77 and 300 K

In this work, we propose a method of calculation for estimating the drift mobility from photoluminescence (PL). The method is based on the difference between the temperature of the scattered carriers after thermalization and the lattice temperature. The effective carrier temperature T_E was determined experimentally by fitting the high-energy region of PL spectra. The total mobility is obtained from the mobility calculated for different scattering mechanisms and the application of the Matthiessen rule. The method was used on InGaAsP semiconducting alloys grown by liquid phase epitaxy. The calculated mobility values for different InGaAsP samples agree with those reported for these alloys.     

High-speed AMHS and its operation method for 300-mm QTAT fab

By using all-single-wafer processing in the 300-mm quick turn-around time production system, we have shortened cycle time to one-half or less than that of mixed-batch processing. We have also developed a high-speed automated material handling systems (AMHS) for achieving short cycle time. An intrabay rail-guided vehicle developed for the 300-mm fab is a component of this system. This paper describes the new system concepts, including AMHS hardware improvement, operation methods, and technician skill enhancement. We achieved a transfer time of one third or less that of previous fabs.     

A time-dependent and two-dimensional numerical model for MOSFET device operation

A time-dependent and multi-dimensional numerical modeling for semiconductor device operation is proposed, in which the quasi-Fermi potentials for electrons and holes rather than the carrier densities are directly analyzed. Fundamental equations for the quasi-Fermi potential are reduced to a diffusion equation that includes a drift term. Boundary conditions are straightforwardly derived from the device physics and are shown in a mathematically simple manner, independent of device structure complexities. From the viewpoint of numerical procedure, a combination of an implicit time integral and upwind difference scheme is adopted. The quasi-Fermi potential is a gradually changing value between the maximum and minimum external applied voltages, and the present method is suitable for numerical modeling.A time dependent and two dimensional analysis program has been developed. The advantages of the present modeling are demonstrated through the carrying out of sample calculations of, for example, MOSFET switching characteristics. Quick and stable convergence in the numerical scheme has been obtained over the range of practically used operation voltages.     

A new model of switching operation in fully depleted ultrathin-filmCMOS/SIMOX

An analysis is made of the switching performances of fabricated ultrathin-film submicrometer-gate CMOS/SIMOX ring oscillators. A time-dependent gate capacitance model is proposed to explain the switching operation mechanism. It is found that reducing the gate capacitance by full depletion of the body silicon dramatically improves the propagation delay time of CMOS/SIMOX     

Cross-sectional TEM of Pd/InP and Au/lnP interfaces formed at substrate temperatures near 300 and 77K

Depositing Pd or Au on InP at cryogenic substrate temperatures has previously been found to significantly increase the barrier height of the resulting Schottky diode. In this work, cross-sectional transmission electron microscopy was used to determine the structural differences between metal/semiconductor (MS) interfaces formed at 300K (RT) and at 77K (LT). In the Pd/lnP case, RT samples exhibited a thick amorphous interaction layer at the MS interface, while LT samples only had a thin phosphorous-rich interfacial layer. However, in the Au/InP case, no amorphous interlayers were observed in any of the samples. Instead, a small amount of Au was found to extend into the InP lattice in the RT case which was not present in LT samples. The thermal stability of the barrier height was studied as well. LT Au/lnP samples were found to exhibit a distinct barrier height shift when annealed at 200°C which was linked to a grain coarsening in the polycrystalline Au layer at this temperature. X-ray diffraction was used to verify changes in the polycrystalline metal's average grain size. We conclude that a significant reduction in the interaction between the deposited metal and InP was responsible for the greatly enhanced barrier height observed in LT interfaces.     

非对称异质双栅应变硅MOSFETs 二维模型研究

基于对二维泊松方程的精确求解,本文对全耗尽型非对称异质双栅应变硅MOSFET的二维表面势,表面电场,阈值电压进行了研究。模型结果和二维数值模拟器的结果很吻合。此外并对该器件的物理作了深入的研究。该模型对设计全耗尽型非对称异质双栅应变硅MOSFET器件有着重要的指导作用.