Vertical p-n-p for Complementary Bipolar Technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose bolon-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.     

Self-aligned complementary bipolar technology for low-powerdissipation and ultra-high-speed LSIs

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit     

Heavy doping effects in p-n-p bipolar transistors

This paper presents the heavy doping effects on the injection current characteristics in p-n-p transistors with a heavily doped but thin base region. The results of the present study indicate that 1) at room temperature the hole current injected into heavily doped base is insensitive to the impurity compensation effect, 2) a linear relationship between the base sheet resistance and the collector-current density is observed when the base doping density is under 1 × 10¹⁹cm^-3. This relationship becomes supralinear as the doping density further increases. As a result, useful current gain exists in thin base transistors even when the base doping is greater than 1 × 10¹⁹cm^-3. From the collector-current-base sheet-resistance relationship and the base doping profile, the effective intrinsic carrier density as a function of the doping density is evaluated and found to increase 8.7 times over that of pure silicon, when the average doping density is 5 × 10¹⁹cm^-3(maximum doping density 1 × 10²⁰cm^-3). 3) The collector current and the current gain of the transistors become less sensitive to the temperature as the base doping density increases. We had observed a current gain up to 30 at 77 K for transistors with the maximum base doping density in the 10¹⁸cm^-3range. The transistors with lower base doping suffer much more degradation in current gain when the temperature is lowered to 77 K.     

p-n-p heterojunction bipolar transistors with buried subcollectorlayers

The buried-layer technology was applied to the fabrication of high-speed p-n-p AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The subcollector layer was selectively implanted prior to the epitaxial growth of the rest of the device structure thereby eliminating the need for deep mesa isolation. Devices with 2×10-μm² emitter fingers and 100-nm base thickness had common-emitter current gains of 15 and cutoff frequencies of 17 GHz     

The performance potential of p-n-p heterojunction bipolar transistors

The performance of P-n-p AlGaAs/GaAs heterojunction microwave and switching transistors is compared to that of N-p-n structures. The maximum frequency of oscillation calculated for an optimized P-n-p microwave transistor is found to be only 29 percent less than that for an optimized N-p-n device. Similarly, the switching time of a P-n-p in a digital circuit is found to be only 28 percent greater than that of an N-p-n. These results are explained in terms of the parameters of a compact transistor model. The potential for use of the P-n-p HBT in microwave and switching applications is discussed in light of both performance and fabrication details.     

A fully planar p-n-p heterojunction bipolar transistor

The fabrication of fully planar p-i-n heterojunction bipolar transistors is reported. The devices were constructed using ion implantation into AlGaAs/GaAs heterostructures grown by metalorganic chemical vapor deposition (MOCVD). Incremental current gains of 100 have been observed for transistors with 22 μm×4 μm emitters, No emitter size effects was observed     

High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Lateral p-n-p bipolar junction transistors (BJTs) fabricated using a bulk 0.25 μm CMOS technology are presented. The devices are structurally the same as p-MOSFETs in which the gate and the n-well are internally connected to form the base. The p-n-p BJT has an adjustable current gain which can be higher than 1000 and its peak cutoff frequency is 3.7 GHz. Since the lateral p-n-p BJT is fully process compatible with submicrometer CMOS and/or BiCMOS technologies, extension to a BiCMOS and/or complementary BiCMOS process is readily achieved     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

A complementary bipolar technology family with a VerticallyIntegrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP^TMI) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies     

高性能纵向pnp晶体管的研制

pnp晶体管中由于空穴的迁移率较电子的迁移率低得多,再加上纵向pnp管有比npn管严重得多的基区宽度调变效应,一般情况下,难以使纵向pnp管的性能与npn管的性能相媲美。我们从理论上分析了提高纵向pnp管性能的途径,并设计了一套新的工艺流程。在p型外延材料上研制出了BV_(ceo)≥90V、V_(be)≤0.8V、f_T=900MHz、V_(ces)=0.2V、β=60～150、厄利电压大于150V的纵向pnp晶体管。在P型单晶材料上研制出了BV_(ceo)≥65V、f_T≥560MHz、β=60～150的纵向pnp晶体管。具有这种性能的纵向pnp管目前在国内外还很少见。     

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

The implementation of high voltage vertical bipolar transistors in a BiCMOS technology requires sufficient space for the extension of the collector-base depletion region. Assuming that layout design rules for high voltage devices are used, the open base breakdown voltage BV_ceo is only defined by the one-dimensional vertical doping profile through the n⁺-emitter, the p-base, the n-intrinsic and the n⁺-extrinsic collector, i.e. lateral effects can be neglected for this type of brakdown. This paper describes the derivation of simple equations for optimizing the n⁺pn⁻n⁺-structure. Closed-form analytical equations based on the impact ionization model from Fulop ([1] Solid St. Electron. 10, 39 (1967)) yield the dependence of the open base breakdown voltage BV_ceo on the transistor gain, doping level and width of the intrinsic collector.     

Integrated complementary HBT microwave push-pull and Darlingtonamplifiers with p-n-p active loads

The authors report the microwave results of complementary heterojunction bipolar transistor (HBT) amplifiers that integrate both n-p-n and p-n-p devices on the same chip using selective molecular beam epitaxy (MBE). An HBT wideband amplifier utilizing the Darlington configuration and implementing a p-n-p active load has a gain of 7.5 dB and a bandwidth from DC to 2.5 GHz. A complementary push-pull amplifier has a saturated output power of 7.5 dBm at 2.5 GHz     

High-performance p-n-p AlGaAs/GaAs heterojunction bipolar transistors: A theoretical analysis

The AlGaAs/GaAs P-n-p heterojunction bipolar transistor (HBT) is shown by a simple analysis to exhibit millimeter wave and digital switching performance comparable to similar N-p-n structures. For example, a P-n-p HBT with a 1-µm emitter stripe and 34-µm²total area yieldsf_{tau} = 31GHz,f_{max} = 94GHz, and an intrinsic switching speedtau_{s} = 8ps. A similar N-p-n structure exhibitsf_{tau} = 56GHz,f_{max} = 102GHz, andtau_{s} = 8ps.     

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p doubleheterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f_T and f_MAX values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

The design and optimization of high-performance, double-polyself-aligned p-n-p technology

The device design and performance of double-poly self-aligned p-n-p technology, featuring a low-resistivity p⁺ subcollector, thin p-epi, and boron-doped poly-emitter are described. Device isolation is provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (⩾40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm and base widths of less than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were obtained, and the AC performance was demonstrated by an NTL-gate delay of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. The matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits     

Bulk silicon technology for complementary MESFETs

A technology for fabrication of complementary silicon MESFETs on bulk silicon substrates has been developed. The technology is similar to CMOS technology, and utilises n-silicon substrates. P-wells are used for the n-channel devices. Device isolation was achieved by trench etching. The silicides of Er and Pt were used as gate Schottky contacts. P- and n-channel characteristics are presented together with subthreshold behaviour and preliminary results regarding radiation hardness. Also, results from two-dimensional simulations of the devices are presented.<>     

Heterostructure complementary technology

A complementary inverter configuration based on two new heterostructure field-effect devices is proposed. The FETs are fabricated in a common substrate grown by molecular-beam epitaxy. The devices rely on the formation of inversion layers at heterojunction interfaces.     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²     

Vertical bipolar transistors in laser-recrystallized polysilicon

Vertical bipolar n-p-n transistors with a base width of 0.2 µm have been fabricated in laser-recrystallized polysilicon films on thermally oxidized silicon substrates. With proper hydrogen annealing steps, common-emitter current gains on the order of 100 were possible. Recombination in the base-emitter space-charge region was found to be the dominant source of base current.