On the Development of an Integrated CMOS-Based UWB Tunable-Pulse Transmit Module

A novel low-cost low-power fully integrated tunable transmit module composed of a tunable CMOS monocycle pulse generator and compact uniplanar antenna was designed, built, and tested for ultra-wideband (UWB) impulse systems. The CMOS tunable pulse generator integrates a tuning delay circuit, square-wave generator, impulse-forming circuit, and pulse-shaping circuit in a single chip using a standard low-cost 0.25-$muhbox m$CMOS process. It can generate a monocycle pulse and Gaussian-type impulse (without the pulse-shaping circuitry) signals with tunable pulse duration. A compact uniplanar UWB antenna was also developed and integrated directly with the CMOS pulse generator chip to form the complete integrated tunable UWB transmit module. Measured results show that the CMOS tunable pulse generator can produce a 0.3–0.6-V peak-to-peak monocycle pulse with 140–350-ps tunable pulse duration and a 0.5–1.3-V peak-to-peak impulse signal with 100–300-ps tunable pulse-duration, and the uniplanar antenna has less than a 18-dB return loss and is suitable for transmitting/receiving UWB time-domain impulse signals covering the entire UWB bandwidth of 3.1–10.6 GHz. Good agreement between measured and calculated performance is also achieved. The UWB transmit module was experimentally characterized and its performance is verified. This UWB module finds applications in various time-domain UWB systems including wireless communications and radar.     

A 0.25-mm CMOS T/R switch for UWB wireless communications

A T/R switch, fabricated using standard 0.25-/spl mu/m CMOS process, for ultra wide-band (UWB) wireless communications is presented. The switch is designed based on the concept of synthetic transmission line, utilizing both CPW and CMOS transistors, to achieve not only an extremely wide bandwidth but also a linear phase response necessary for time-domain UWB applications. On-chip measurement is completed in both frequency and time domains. Frequency-domain measured results show insertion loss of 2.2-4.2 dB, isolation from 34-48 dB, and highly linear transmission phase from 0.45 MHz to 13 GHz. These results are quite consistent with the calculations. Particularly, the time-domain pulse measurement shows that the output pulses resemble closely the input pulses with very little reflection, demonstrating the switch's suitability for true time-domain UWB applications. The developed switch is ready to be integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation

A new circuit technique, the distributed waveform generator (DWG), is proposed for low-power ultra-wideband pulse generation, shaping and modulation. It time-interleaves multiple impulse generators, and uses distributed circuit techniques to combine generated wideband impulses. Built-in pulse shaping can be realized by programming the delay and amplitude of each impulse similar to an FIR filter. Pulse modulation schemes such as on-off keying (OOK) and pulse position modulation (PPM) can be easily applied in this architecture. Two DWG circuit prototypes were implemented in a standard 0.18 $muhbox{m}$ digital CMOS technology to demonstrate its advantages. A 10-tap, 10 GSample/s, single-polarity DWG prototype achieves a pulse rate of 1 GHz while consuming 50 mW, and demonstrates OOK modulation using 16 Mb/s PRBS data. A 10-tap, 10 GSample/s, dual-polarity DWG prototype was developed to generate UWB pulses compliant with the transmit power emission mask. Based on the latter DWG design, a reconfigurable impulse radio UWB (IR-UWB) transmitter prototype was implemented. The transmitter's pulse rate can be varied from 16 MHz range up to 2.5 GHz. The bandwidth of generated UWB pulses is also variable, and was measured up to 6 GHz (${- 10} {rm dB}$ bandwidth). Both OOK and PPM modulation schemes are successfully demonstrated using 32 Mb/s PRBS data. The IR-UWB transmitter achieves a measured energy efficiency of 45 pJ/pulse, independent of pulse rate.      

Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

A resonant switch for LNA protection in watt-level CMOS transceivers

An integrated resonant switch designed to protect low-noise amplifier (LNA) circuits in CMOS transceivers is reported. The design implements the receive-path portion of a transmit/receive switch protecting 3-V-process transistors from 5 W (22-V peak) transmit signals while simultaneously helping to achieve a good LNA noise figure on receive and low power loss on transmit. Since the approach is to combine an LNA's matching network and switch functions, the design has no traditional insertion loss on receive. The effective loss to the transmitted signal is less than 0.5 dB using moderate quality inductors (Q>6) and 0.1 dB using Q=12 inductors achievable in most RF-aware CMOS silicon-on-insulator foundries at UHF through S-band frequencies.     

A sub-nanosecond resonant-type monolithic T/R switch formillimeter-wave systems applications

This paper is concerned with the design consideration, fabrication process, and performance of a V-band monolithic transmit/receive (T/R) switch for millimeter-wave wireless networks applications. The developed switch integrated circuit (IC) has a novel structure in which to pass a signal, it presents a parallel resonant circuit to the signal by forward biasing a pair of switching heterojunction FET's (HJFETs), but to block the signal, it presents a series resonant circuit to the signal by reverse biasing the switching HJFETs. With a control voltage of 0/3.2 V, the developed T/R switch exhibits a minimum insertion loss of 3.9 dB, a maximum isolation of 41 dB, and a high switching speed of 250 ps, over 57-61 GHz. The monolithic T/R switch chip size is 3.3 mm×1.7 mm     

A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process

A 30 dBm ultra-low insertion loss CMOS transmit-receive switch fully integrated with an 802.11b/g/n transceiver front-end is demonstrated. The switch achieves an insertion loss of 0.4 dB in transmit mode and 0.1 dB in receive mode. The entire receiver chain from antenna to baseband output achieves a measured noise figure of 3.6 dB at 2.4 GHz. The switch has a P_1dB greater than 30 dBm by employing a substrate isolation technique without using deep n-well technology. The switch employs a 1.2 V supply and occupies 0.02 mm² of die area.     

一种有载频超宽带脉冲源设计

针对无载频脉冲低频分量大、辐射效率低、频带可调性差等问题,设计了一种以阶跃恢复二极管、D触发器及超宽带调制器为主的宽频带、高重复频率、低振铃水平的有载频超宽带脉冲源。该脉冲源电路由驱动电路、高速开关电路、整形电路、超宽带调制器及振荡器电路组成。实测结果表明,脉冲源输出脉冲信号重复频率可达125 MHz,脉冲宽度600 ps（底宽）,脉冲振铃水平低于10%,峰-峰值为5.4 V,-10 dB带宽可达4.2 GHz。脉冲信号中心频率与载频相同,可在6.6~8.5 GHz之间灵活设置。利用所设计的脉冲源进行时域测量,其结果与矢量网络分析仪频域测量结果相比幅频特性均方根误差小于0.21 dB。该脉冲源可应用于超宽带时域测量、短距离高速无线通信、高精度室内定位等应用。     

A CMOS UWB Pulse Generator for 6–10 GHz Applications

A CMOS ultra wideband (UWB) pulse generator with low energy dissipation and high peak amplitude is presented for 6–10 GHz applications. The pulse generator complies with the FCC spectral mask for indoor UWB systems. It consists of a glitch generator, a pulsed oscillator, and a pulse shaping filter. The pulsed oscillator is switched on by the glitch signal only for a short duration, so as to make a UWB pulse. For sub-nanosecond pulse generation, a pulsed oscillator with fast transient response is proposed. A pulse shaping filter makes the oscillator output fall into the FCC spectral mask. The pulse generator is fabricated using a 0.18 $mu$ m CMOS process. The core chip has a size of 0.11 mm $^{2}$. It shows pulse duration of about 500 ps with ${-}10$ dB bandwidth of 4.5 GHz from 5.9 to 10.4 GHz. The energy consumption is 27.6 pJ per pulse with a peak-to-peak amplitude of 673 mV on a 50 $Omega$ output load. The generated pulses are very coherent with 1.8 ps RMS jitter.      

20 GHz Wavelet Generator Using a Gated Tunnel Diode

We demonstrate the use of a GaAs-AlGaAs gated tunnel diode (GTD) in an ultra-wideband (UWB) wavelet generator. An inductor is integrated to form an oscillator circuit, which is driven by the negative differential conductance property of a GTD. It is demonstrated that as the gate tunes the magnitude of the output conductance, the oscillator may be switched on and off, creating short RF pulses. The shortest pulses generated are 500 ps long, the highest output power for the free running oscillator is $-$4.1 dBm, and the highest oscillation frequency is 22 GHz. Analytical expressions based on the van der Pol equation describing the pulse length and amplitude are presented. This technique is applicable for high frequency impulse radio UWB implementations.      

Power-efficient switching-based CMOS UWB transmitters for UWB communications and Radar systems

This paper presents a new carrier-based ultra-wideband (UWB) transmitter architecture. The new UWB transmitter implements a double-stage switching to enhance RF-power efficiency, reduce dc-power consumption, and increase switching speed and isolation, while reducing circuit complexity. In addition, this paper also demonstrates a new carrier-based UWB transmitting module implemented using a 0.18-/spl mu/m CMOS integrated pulse generator-switch chip. The design of a UWB sub-nanosecond-switching 0.18-/spl mu/m CMOS single-pole single-throw (SPST) switch, operating from 0.45 MHz to 15 GHz, is discussed. The design of a 0.18-/spl mu/m CMOS tunable impulse generator is also presented. The edge-compression phenomenon of the impulse signal controlling the SPST switch, which makes the generated UWB signal narrower than the impulse, is described. Measurement results show that the generated UWB signal can vary from 2 V peak-to-peak with 3-dB 4-ns pulsewidth to 1 V with 0.5 ns, covering 10-dB signal bandwidths from 0.5 to 4 GHz, respectively. The generated UWB signal can be tuned to cover the entire UWB frequency range of 3.1-10.6 GHz. The sidelobe suppression in the measured spectrums is more than 15 dB. The entire CMOS module works under a 1.8-V supply voltage and consumes less than 1 mA of dc current. The proposed carrier-based UWB transmitter and the demonstrated module provide an attractive means for UWB signal generation for both UWB communications and radar applications.     

A Fully Differential Digital CMOS UWB Pulse Generator

A new fully digital CMOS pulse generator for impulse radio ultra-wideband (UWB) systems is presented. First, the shape of the pulse which best fits the FCC regulation in the 3.1–5 GHz sub-band of the entire 3.1–10.6 GHz UWB bandwidth is derived and approximated using rectangular digital pulses. In particular, the number and the width of pulses that approximate an ideal template are found through an ad hoc optimization methodology. Then a fully differential digital CMOS circuit that synthesizes the pulse sequence is conceived and its functionality demonstrated through post-layout simulations. The results show a very good agreement with the FCC requirements and a low power consumption.     

瞬时超宽谱多脉冲产生技术研究

通过对国内外瞬时多脉冲产生技术的调研,结合超宽谱脉冲的特点,开展了三种瞬时超宽谱多脉冲产生技术研 究。脉冲分割方式由于需要多个开关,而每个开关都存在一定的导通电感和导通电阻,会导致被分割的脉冲前沿变缓, 同时幅度变小;形成线串联方式虽然存在开关电容、隔离电感等的影响,但通过优化获得了较稳定的双脉冲输出;多脉 冲合成方式利用磁性材料的特殊性能来传输和隔离脉冲,但现有的一些磁性材料的响应速度不够,即在ns 脉冲下,磁芯 的工作点来不及变化,并未起到磁隔离的作用。     

16.6- and 28-GHz Fully Integrated CMOS RF Switches With Improved Body Floating

This paper presents two fully integrated CMOS transmit/receive (T/R) switches with improved body-floating operations. The first design exploits an improved transistor layout with asymmetric drain-source region, which reduces the drain-source feed-through for body-floated RF switches. In the second design, a switched body-floating technique is proposed, which reconfigures the body-floating condition of a switch transistor in the ON and OFF states. Both designs are fabricated in a standard 0.13-mum triple-well CMOS process. With regard to 2-dB insertion loss, the switch with asymmetric drain-source achieves 28-GHz bandwidth, which is among the highest reported frequencies for CMOS T/R switches. The bandwidth of the switched body-floating design is 16.6 GHz. There is approximately 5 dB better isolation obtained in the switched body-floating design. With the resistive double-well body-floating technique, 26.5- and 25.5-dBm input 1-dB compression point (P_1dB) are obtained, respectively. Both designs consume only 150 mum times 100 mum die area. The demonstrated T/R switches are suitable for high-frequency and wideband transceivers.     

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

This paper presents a novel impulse radio based ultra-wideband transmitter. The transmitter is designed in 0.18 mum CMOS process realizing extremely low complexity and low power. It exploits the 6-to-10 GHz band to generate short duration bi-phase modulated UWB pulses with a center frequency of 8 GHz. No additional RF filtering circuits are required since the pulse generator circuit itself has the functionality of pulse shaping. Generated pulses comply with the FCC spectral emission mask. Measured results show that the transmitter consumes 12 pJ/b to achieve a maximum pulse repetition rate of 750 Mb/s. An optional embedded on-chip antenna and a power amplifier operating in 6-10 GHz band are also designed and investigated as a future low cost solution for very short distance IR-UWB communications.     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。