Robust analogue background calibration technique for multi-bit switched capacitor DACs

A robust analogue calibration technique to continuously correct for element mismatch in multi-bit switched capacitor DACs is proposed. Unlike most existing analogue calibration techniques, its accuracy is not limited by the mismatch of charge injection that is outside of the calibration loop. Using the proposed technique, multi-bit switched-capacitor DACs the linearity of which is only limited by the calibration loop gain can be realised. Simulation results show that the INL of a switched-capacitor DAC improves from 8-bit level to 15-bit level with the proposed calibration.     

一种SAR ADC电容失配自测量与数字校准技术

为了解决高分辨率逐次逼近模数转换器(SAR ADC)中,电容式数模转换器(DAC)的电容失配导致精度下降的问题,提出了一种电容失配自测量方法,以及一种可适用于各种差分电容DAC设计的低复杂度的前台数字校准方法。该方法利用自身电容阵列及比较器完成位电容失配测量,基于电容失配的转换曲线分析,对每一位输出的权重进行修正,得到实际DAC电容大小对应的正确权重,完成数字校准。数模混合电路仿真结果表明,引入电容失配的16位SAR ADC,经该方法校准后,有效位数由10.74 bit提高到15.38 bit。     

双采样技术在三阶sigma-delta调制器中的应用

近年发展的双采样技术（ｄｏｕｂｌｅ ｓａｍｐｌｉｎｇ）是提高ｓｉｇｍａ－ｄｅｌｔａ调制器信噪比的一种有效的方法,而电容的失配是影响其信噪比的重要因素。分析表明,双采样技术在三阶系统中的应用,电容失配引起前馈信号混叠,由此产生的噪声对系统信噪比的影响不可忽略。本文提出了一种结合ＩＬＡ ＤＡＣ「２」和前端完全浮动电容结构的电路形式,将这种结构应用在第二级调制器的积分器上,使双采样电容失配产生的噪声远小     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

Mismatch shaping for a current-mode multibit delta-sigma DAC

Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (ΔΣ) modulators are reviewed, and a mismatch-shaping technique for bandpass ΔΣ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time ΔΣ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques     

对电容失配不敏感的MDAC结构与技术

根据电荷守恒原理对MCS（merged-capacitors switching）技术的原理进行了详细地阐述与分析。分析结果表明,采用MCS技术的MDAC除了需要信号地外,与传统MDAC在功能上是一致的,而且,在速度与功耗保持不变的情况下,可获得更高的电容匹配精度,从而降低了MDAC对电容失配的敏感度。此外,结合MCS技术和CFCS（commutated feedback capacitor switching）技术,提出了一种低DNL1．5位MDAC。数学分析表明,与典型的1．5位MDAC相比,所提出的1．5位MDAC中的电容失配对流水线ADC的DNL的影响明显减小且只需增加—个多路选择器,电路实现仍然简单,速度与功耗也维持不变。     

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.     

Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method

A dynamic element-matching (DEM) method, i.e., randomized thermometer coding (RTC), for low-cost current-steering digital-to-analog converter (DAC) design is proposed. The proposed RTC method exhibits randomized starting-element selection, consecutive-element selection, and low-element switching activity. It can be used to significantly suppress the harmonic distortion caused by a large mismatch of small-area transistors, and, thus, very low cost DACs can be realized. With the proposed RTC, a 14-bit current-steering DAC is implemented in a 1P6M 0.18- $muhbox{m}$ 1.8-V CMOS process. The measured spurious-free dynamic range (SFDR) exceeds 80 dB. The measurement results showed that RTC improves the SFDR by more than 16 dB. The DAC has an active area of less than 0.28 $hbox{mm}^{2}$. The proposed DAC achieves a smaller active area than state-of-the-art 12- to 14-bit DACs.      

应用于高速SAR ADC的高能效开关方案

介绍了一种应用于高速逐次逼近型模数转换器的新型高能效电容开关方案。基于2bit/cycle结构,采用两个分裂电容阵列作为数模转换器。通过单边充电操作,在减小电容阵列动态功耗和总面积的同时,提高了电容的建立速度。在最后一个量化周期中,只在电容阵列的单边引入共模电压基准,并只用一个比较器参与量化,在获得更高精度的同时,进一步降低了电容阵列的动态功耗。相比传统1bit/cycle电容开关方案,该新型电容开关方案在提升系统量化速度约2倍的同时,降低了电容阵列平均功耗83%,减小了电容总面积50%。相比其他2bit/cycle开关方案,在精度、电容总面积和功耗方面均有不同程度的改善。     

一种10位电容电阻混合型双极性D/A转换器

在加速度计中,需要数模转换器(DAC)提供一个稳定的偏压来消除重力加速度,要求DAC具有高精度、单调性和小面积等特性。为了解决传统电阻型DAC存在的大面积和传统电容DAC中存在的非单调性等问题,提出了一种电容电阻混合型DAC结构,并设计了一个10位的DAC,用于提供稳定偏压。提出一种新的电容共质心的版图布局,提高了DAC的精度。该DAC在0.5μm CMOS工艺上得以验证实现,微分非线性误差(DNL)最大为0.50LSB,积分非线性误差(INL)最大为0.82LSB,在5V和-5V的双电源供电条件下,芯片功耗为16mW,完全满足了工程需求。     

A First-Order Tree-Structured DAC With Reduced Signal-Band Noise

A mismatch-shaping tree-structured digital-to-analog converter (DAC) utilizes several layers of switching blocks to spectrally shape the DAC circuit errors. A first-order mismatch-shaping DAC using un-dithered switching sequences for the switching blocks results in spurious tones in the DAC noise. The unwanted tones can be eliminated from the DAC noise by employing white dither sequences to randomly select two types of short root symbols to be placed in the switching sequences. Dithered switching sequences, unfortunately, result in a higher noise floor in the DAC noise, in comparison with un-dithered switching sequences. In this brief, we propose an improved first-order sequencing logic to eliminate unwanted tones while causing only a modest increase in the in-band noise floor at a very modest hardware cost. Our mismatch-shaping sequencing logic is based on the scheme using a white dither sequence to randomly select each symbol between two specific types of long root symbols. Alternatively, our scheme can be viewed as using a high-pass dither sequence to randomly select the short root symbols. An analytical formula for the power-spectral density of the proposed switching sequence is presented to show its improvement over the prior first-order switching sequence. It is also shown from numerical simulations that the proposed switching sequence improves the signal-to-noise plus distortion ratio by more than 5 dB for a sigma-delta modulator with static DAC-element errors chosen from a Gaussian distribution with a standard deviation of 1%     

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.     

High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

一种应用于48V-1V系统的隔离型混合模式降压变换器

提出了一种应用于48 V-1 V系统的隔离型混合模式降压变换器,利用飞电容和变压器实现高转换比应用下的高转换效率。混合变换器结合了开关电容变换器和开关电感变换器,其中飞电容承担了部分电压降,实现了功率开关管电压应力的降低。由于开关节点处的电压摆幅较小,开关损耗随之减小;通过使用更低压的功率开关管,实现功率开关管导通损耗减小。在此基础上,隔离型混合模式降压变换器通过时序控制可以实现软开关,进而实现功率开关管开关损耗减小,使得整体效率提升。在隔离型混合模式降压变换器中,飞电容还具有隔直电容的作用,可以防止变压器偏磁。在典型应用下,即在48 V输入电压、1 V输出电压、500 kHz开关频率下,峰值效率为94.84%。     

A two-stage weighted capacitor network for D/A-A/D conversion

A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier is described. The two-stage weighted capacitor DAC requires a smaller range of capacitor values then the conventional weighted capacitor DAC and is not subject to the nonlinear effects of parasitic capacitance. Experimental results of such a DAC implemented using a conventional n-channel metal-gate MOS process are presented. A discussion of the comparative accuracy and area of one- and two-stage weighted capacitor DAC's on the basis of capacitor tracking is given.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

一种单端10-bit SAR ADC IP核的设计

本设计通过采用分割电容阵列对DAC进行优化,在减小了D/A转换开关消耗的能量、提高速度的基础上,实现了一款采样速度为1 MS/s的10-bit单端逐次逼近型模数转换器。使用cadence spectre工具进行仿真,仿真结果表明,设计的D/A转换器和比较器等电路满足10-bit A/D转换的要求,逐次逼近A/D转换器可以正常工作。     

一种新型二分电容DAC的设计

为了进一步减小电容阵列DAC占用的面积,提出了一种可用于SAR ADCs的二分电容阵列(三段电容阵列,T-SC)结构。与传统二段电容阵列相比,提出的二分电容阵列在不增加对电容匹配性要求的前提下,减少了芯片面积。在理论上分析了该结构的电容失配和寄生效应,归纳提出了一种计算电容阵列DAC DNL的简易公式。Matlab仿真结果与理论分析有较好的一致性,三段电容阵列结构能够实现较好的二进制权重特性;根据提出的计算DNL的简易公式进行参数设计,仿真DNL标准偏差为0.51 LSB,与理论计算0.5 LSB相差0.01 LSB。     

High-level modeling of resistor string based digital-to-analog converters

To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented in MATLAB^TM environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects. The model was successfully used to design a 10bit resistor string DAC in a 0.18 μm BCD technology with DNL and INL lower than 1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art.     

一种用于14 bit SAR ADC的DAC设计

本文设计了用于14bit逐次逼近型模数转换器（SAR ADC）的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。