An advanced diagnostic method for delay faults in combinational faulty circuits

Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method.     

Modeling for bridging faults in nMOS combinational circuits

A transistor level model that fully describes the logical behavior of a circuit in the presence of bridging faults is presented for the nMOS combinational circuits. The proposed model is suitable for the circuits having static enhancement/depletion (E/D) load. Thus, the model can be applied to circuits like pseudo nMOS and CMOS non-threshold-logic (NTL). The model employs a logic transistor function (LTF) to examine the behavior of such circuits. The LTF model developed earlier for stuck faults in nMOS circuits is extended for bridging faults. Algorithms that were developed for the stuck faults in pseudo nMOS combinational circuits can be applied to generate the test vectors for bridging faults.     

Modeling and testing for stuck faults in pseudo nMOS combinational circuits

In this paper, a new transistor model is developed. This model employs the logic transistor function (LTF) to examine the behavior of pseudo nMOS logic circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M). I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults are analyzed in the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specified sub circuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used.     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

Power-constrained testing for bridging and stuck short faults in CMOS combinational circuits

An increasing demand for the portable applications has elevated power consumption to be the most critical parameter. A transistor level model and a testing methodology are presented for detected bridging and stuck short faults in CMOS combinatorial circuits, with the power consumption as a major constraint during testing. The circuits are modeled by the CTF (Current Transfer Function) model. The quiescent current (IDDQ) measurement technique is utilized as the testing methodology. Transistor stuck open faults, that can change the test vector for IDDQ, are incorporated in the model. Simulation using hspice is carried out to support the results.     

Diagnosis of single stuck-at faults and multiple timing faults in scan chains

A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented. This technique applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults. With SE patterns, the problem of unknown values in scan chains is eliminated. The diagnosis result is therefore deterministic, not probabilistic. In addition to the first fault, this technique also diagnoses the remaining timing faults by applying multiple excitation patterns. Experiments on benchmark circuits show that average diagnosis resolutions are mostly less than five, even for the tenth fault in the scan chain.     

典型电力电子电路仿真的研究

电力电子技术的关键知识点很多,电路结构变换复杂,但在应用中,典型的电路最为常见,分析好典型电路也就掌握了电力电子技术的核心内容。文中给出了设计思路和仿真方法,详细分析三个经典的电力电子电路,将电路中关键的变量仿真出来,并最终给出了实际的仿真效果图。     

Reconvergent fanout analysis and fault simulation complexity of combinational circuits

The detectability of reconvergent fanout stem faults in a combinational logic circuit can be determined by explicitly simulating the faults within limited regions of the circuit. These regions are defined, and an estimate of the fault simulation complexity of the circuit is obtained. Results are presented for ten benchmark circuits.     

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

模拟电路常见故障的诊断及处理分析

随着科学技术发展日新月异和全民智能化时代的到来,种类繁多的电子产品在人们日常生活中的应用也变得随处可见,从各个方面影响着人们的生活。但是,电子产品在使用过程中也容易受到电路故障的影响而失效。因此,在电子产品电路出现故障时,及时找到故障原因是十分必要的。文章将系统地探寻和分析电路故障的常见诊断方法,达到提升电路故障处理速率的目的,并确保将电路故障带来的损失降至最低。     

基于Matlab仿真的谐振接地系统单相接地故障分析

电力系统中性点接地方式的选择对防止电力系统事故的扩大具有重要意义,谐振接地方式非常有利于电力系统的安全运行。该文对中压电网单相接地故障利用Matlab软件进行仿真,以分析研究在谐振接地方式下,中压电网发生单相接地故障时电力系统的基本运行特性,并结合理论分析结果,给出了谐振接地运行方式的特点及其对电力系统的作用。     

A method for automatic design error location and correction in combinational logic circuits

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size. This work is partially supported by EUREKA “JESSI-AC3” project and the ESPRIT Basic Research Action CHARME Working Group #6018.     

Logical redundancies in irredundant combinational circuits

Some new types of logical redundancies that can occur in a combinational network are investigated. Three kinds of redundancy, namely a-redundancy, b-redundancy and c-redundancy are already well-known. This article presents two new types of redundancy called p-redundancy and n-redundancy in combinational networks which are otherwise known to be irredundant. A combinational circuit is calledp-redundant (n-redundant), if it is possible to realize the same function by permuting (inverting) some input terminals, in the presence of certain stuck-at faults in the circuit.     

Bounding fault detection probabilities in combinational circuits

This paper focuses on the problem of bounding fault detection probabilities in combinational circuits. Two algorithms, the complete cutting algorithm and the gate blocking algorithm, are presented that always produce true lower bounds on the detection probability of a fault. Both algorithms can be used to identify difficult-to-test faults and to quickly construct test sets for specific faults. Both algorithms have qualitative versions which provide insight into a circuit while avoiding arithmetic calculation. Both algorithms resulted from research in trying to determine the accuracy of the safety factor heuristic of Jacob Savir.This research was supported by a grant from the IBM Corporation.     

基于GSAA算法的组合电路最大功耗估计方法

最大功耗估计问题是一个NP难题。提出的方法利用遗传模拟退火算法(GSAA)在整个解空间快速搜索问题的最优解，实现组合电路最大功耗的快速、精确估计。仿真结果表明，提出的方法比基于遗传算法(GA)的估计方法在估算精度和收敛速度上都有提高，适合于大规模组合电路最大功耗的估计。     

Hazard simulation of sequential circuits

A 7-valued logic appropriate for hazard simulation of sequential circuits is investigated in this letter. The 5-valued system of Lin and Reddy is extended to discriminate transitions with and without hazard. We assume that hazards are damped in the feed-back loop of flip-flops, and introduce a kind of filter to assure it. The application to hazard checking is demonstrated for counter circuits.     

Soft error generation analysis in combinational logic circuits

Reliability is expected to become a big concern in future deep sub-micron integrated circuits design.Soft error rate(SER) of combinational logic is considered to be a great reliability problem.Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects,but they failed to achieve enough insights.In this paper,an analytical glitch generation model is proposed.This model shows that after an inflexion point the collected charge has an...     

基于分数阶相关的模拟集成电路软故障诊断* Deng Yong(邓勇), Shi Yibing(师奕兵)and Zhang Wei(张伟)

针对模拟集成电路软故障诊断的难题,提出了基于分数阶相关的方法。首先,利用分数阶小波包将待测试电路(CUT)的Volterra级数进行分解,计算出分数阶相关函数。然后,用得到的分数阶相关函数构造出待测试电路的故障特征。通过对故障特征的比较,可以将待测试电路的各种软故障状态进行辨识并对故障实现定位。标准电路的仿真实验描述了这一方法并验证了该方法对模拟集成电路软故障诊断的有效性。     

组合逻辑电路中的软错误（Soft Error）生成模型的分析

在深亚微米集成电路设计领域,电路可靠性问题日益严重。这个问题的一个重要方面是组合逻辑电路的软错误。现有的关于软错误率的分析和模型表明电压脉冲宽度对电气掩蔽（Electrical Masking）以及锁存窗掩蔽（Latch Window Masking）两种效应都有很大的影响。电压脉冲的宽度通过影响这两种效应进而决定了电路的软错误率。但是这些分析和模型在这个问题上不够深入。在这篇文章中,我们首次提出一个脉冲生成的解析模型。这个模型表明,越过一个拐点后,电路中由射线粒子注入的电荷量同电压脉冲宽度之间存在指数关系。这个模型的平均误差约为2.6%。这个模型还揭示了逻辑门延时与软错误率之间的折中关系。这个关系是最近的一篇有关组合逻辑电路软错误率降低方法的论文的基础[19]。     

红外热像的初始化诊断法

简述通常采用的热平衡后摄取红外热像进行故障诊断所带来的问题和针对该问题所作的试验，试验结果表明初始化诊断法可以有效地抑制通过热传导、热辐射、热对流方式对被测元器件相互间的影响，从而使诊断准确、迅速。