Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

New insights on the post-BD conduction of MOS devices at the nanoscale

We have combined standard electrical tests with conductive-atomic force microscopy experiments to investigate the conduction of MOS devices after the dielectric breakdown (BD) of the SiO/sub 2/ gate oxide. In particular, the influence of the conduction nanometer scale parameters on the overall device post-BD current-voltage characteristics has been analyzed. The results show a nonuniform conductivity of the oxide at the BD area and that the total current flowing through the device is mainly driven by a very small fraction of that region.     

Gate resistance modeling of multifin MOS devices

This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to minimize the gate resistance and RC delay is provided to design multifin MOS devices for high frequency applications.     

Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization

A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.     

Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.     

A test for lateral nonuniformities in MOS devices using only capacitance curves

Capacitance vs voltage (C-V) curves of metal-oxide-semiconductor (MOS) devices are affected both by interface states and by lateral nonuniformities (such as barrier-height or fixed-charge variations across planes parallel to the interface plane). If the doping profile of the device is known, then it is shown that from C-V curves alone one can distinguish between nonuniformity effects and interface state effects. Two ways to make this distinction are described and tried experimentally. One method uses the quasi-static C-V curve to determine the interface-potential, ψ, and the high-frequency C-V curve to determine the depletion width, w. Then this experimental w-ψ relation is compared with the w-ψ relation expected for the known doping profile. Any discrepancy can be due only to nonuniformities. The second (preferred) approach is to use the quasi-static and high-frequency C-V curve to determine an apparent doping profile corrected for interface-states. This apparent profile is then compared with the known profile. Again, only nonuniformities can cause the two profiles to differ.Our method of detecting nonuniformities is also useful in assessing whether it is the interface state density or the interface uniformity which is altered during a given fabrication or aging process performed upon an MOS device. If a quasi-static and a high-frequency C-V curve are measured both before and after the process under study, then “before” and “after” apparent doping profiles (or w-ψ relations) can be compared. Any difference between the “before” and “after” profiles can be interpreted in terms of an effect of the process upon device uniformity.Experimental measurements on devices known to be nonuniform show the method to be viable at least for gross nonuniformities.     

Accuracy of conventional inversion charge modeling in scaled down MOS devices

The density of surface inversion charge in MOS structures is typically calculated using the relation Q = cox(V_G − V_T). In the present article we try to quantitatively assess the goodness of this relation in the case of MOS devices scaled down according to constant field scaling and constant voltage scaling principles by comparing the inversion charge given by this relation to the inversion charge obtained by numerically solving the Poisson equation in one dimension. It turns out that while in the case of constant field scaling the conventional relation for inversion charge becomes progressively erroneous, the same is not true for devices scaled down according to constant voltage scaling.     

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10^-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.     

Error analysis of high-frequency MOS capacitance calculations

An error analysis of the Lindner and Grove et al. methods of computing the high-frequency capacitance of metal-oxide-semiconductor (MOS)_capacitors is presented. The analysis is based upon a differential equation for the capacitance introduced by Sah, Pierret and Tole (the “SPT capacitance”). This equation does not employ the minority-carrier-depletion approximation of Lindner, nor the depletion-width approximation of Grove et al., nor does it require matching different solutions in different bias regions. Consequently, all these approximations can be tested.Our results show that the approximations in the Lindner capacitance introduce only $\text{1}\text{to}\text{2}\text{1}\text{2}$ per cent deviation from the SPT capacitance in the doping range from 10¹⁷/cm³ to 10¹³/cm³, respectively. The simple Grove capacitance based upon the majority carrier depletion approximation differs by 10 per cent from the SPT capacitance at a band bending 5 kT/q on the depletion side of flatbands, and differs by 6–11 per cent in strong inversion for the same doping range. Finally, it is shown that by resorting to a numerical integration the Lindner capacitance can be made to agree with the SPT capacitance to 10^?10C_FB at 10¹⁷/cm³ and 10^?5C_FB at 10¹³/cm³ (C_FB = flatband capacitance). These results indicate that the SPT calculation is rather well approximated by the Lindner capacitance, and that for most purposes some form of the Lindner capacitance would be adequate.Our results also indicate the level of accuracy that is meaningful in any numerical evaluation of the various calculations.Finally, it should be noted that errors due to overidealizations in the SPT formulation itself have not been evaluated. However, whatever this error may be, the net error in any of the other methods is the sum of the SPT error and the error computed here. Consequently, any future error analysis need not repeat what has been done here, but may confine itself to the error in the SPT calculation.     

Exact capacitance of a lossless MOS capacitor

First order Ricatti equations are obtained for the capacitive 3-wire transmission line of a one-dimensional MOS capacitance which give an order of magnitude improvement in numerical computation time over the transmission matrix solution of the lumped section equivalent circuit model of the transmission line.     

New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.     

Direct capacitance measurements of small geometry MOS transistors

Methods for measuring the intrinsic capacitances of small geometry MOS transistors are described. The influence of short- and narrow-channel effects on the capacitance characteristics of MOS transistors is evaluated. The results are compared with long-channel devices. It is shown that the presented capacitance methods can be used to study the physics of short-channel transistors.     

Mathematical modeling of nanoscale MOS capacitance in the presence of depletion and energy quantization in a poly-silicon gate

A model has been developed to study the effect of depletion and energy quantization at the poly-silicon/oxide interface on the behavior ofa nanometer scale n-MOSFET. A model of inversion charge density, including the inversion layer quantization using the variation approach in the substrate, has also been produced. Using the exact calculations of the polygate potential under the depletion and quantization conditions, a C-V model has been devel-oped. All the results have been compared with the numerical models reported in existing literature and they show good agreement.     

Mathematical modeling of nanoscale MOS capacitance in the presence of depletion and energy quantization in a poly-silicon gate

A model has been developed to study the effect of depletion and energy quantization at the poly-silicon/oxide interface on the behavior of a nanometer scale n-MOSFET. A model of inversion charge density including the inversion layer quantization using the variation approach in the substrate has also been done. Using the exact calculations of the polygate potential under the depletion and quantization conditions, a C-V model has been developed and all the results have been compared with the numerical models reported in existing literature show good agreement.     

Stress-sensitive properties of silicon-gate MOS devices

Stress-sensitive properties were measured on both p- and n-channel silicongate MOS devices fabricated on (100) Si at room temperature. Stress-induced variations in drain currents for both enhancement- and depletion-mode MOS transistors with various channel-dopings were measured over a wide range of gate biases. In addition to piezoresistance effect, remarkable drain-current variations were observed at weak-inversion and explained theoretically in terms of changes in minority carrier densities due to energy band shifts by stresses. Elastoresistance shear-constants for polycrystalline-silicon gate layers were also obtained and compared with coefficients for source-drain diffused layers. Further, the elastoresistance of p-type polycrystalline-silicon films was investigated on doping-concentration dependences. A theoretical model for polycrystalline-silicon elastoresistance was developed based on the barrier model for conductivity in polycrystalline-silicon. Results obtained from the model were compared with the experimental results and found to be in good agreement at higher doping-concentrations than trap density.     

The effects of oxide traps on the MOS capacitance

The trapping of electrons and holes at a semiconductor surface by traps located in the oxide adjacent to the semiconductor has been considered. It is shown that the effective capture cross section of an oxide trap viewed by a carrier at the semiconductor surface is reduced by a factor which increases exponentially with the distance the trap is located from the interface. A pseudo-Fermi function in this position variable is developed which gives the probability that a trap will be filled (or emptied) in a measurement time, Tm. The trapping kinetics developed in the first part of the paper are applied to yield the full frequency and bias dependence of an MOS capacitor for an arbitrary spatial and energy trap distribution. Specific examples are given and the problem of voltage hysteresis is dealt with quantitatively. The conclusion is that very little information about the energy distribution and capture cross sections of the oxide traps is obtained from the analysis of MOS-capacitance curves.     

Limitations of quasi-static capacitance models for the MOS transistor

This letter compares the Meyer [1] and Ward [2,3] quasi-static, intrinsic capacitance formulations for the MOS transistor to an exact, non-quasi-static, incremental analysis of a simplified device. This analysis yields an incremental admittance matrix for the device whose terms are ratios of power series. The Meyer and Ward models are shown to be approximations to this exact solution. Experimental admittance versus frequency data are presented which show good agreement with this theory. The high-frequency modeling of the Ward and Meyer formulations are compared to the data above, and the limitations of these models are discussed.     

Inversion charge redistribution model of the high-frequency MOS capacitance

The high-frequency semiconductor capacitance in an MOS structure is ordinarily calculated by a depletion-charge analysis approach assuming that there is no response of the inversion layer charge to the a.c. signal. The more realistic model, in which the inversion charge is allowed to be spatially redistributed at the high frequency, is treated here by the solution of the Poisson-Boltzmann equation incorporating an appropriate quasi-Fermi level for the inversion layer carriers. The inclusion of this effect leads to a much faster saturation of the capacitance and increases the value at strong inversion by 2–5 per cent for silicon at room temperature. It also predicts a shallow minimum less than 1 per cent below the asymptotic value. Agreement with experiment is shown to be excellent. An analytic expression for the asymptotic value is given.