Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

在SiO2中掺Al对Au/纳米(SiO2/Si/SiO2)/p-Si 结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米(SiO2/Si/SiO2)/p-Si结构和纳米(SiO2∶Al/Si/SiO2∶Al)/p-Si结构,用磁控溅射制备纳米SiO2∶Al时所用的SiO2/Al复合靶中的Al的面积百分比为1%．上述两种结构中Si层厚度均为1—3nm,间隔为0.2nm．为了对比研究,还制备了Si层厚度为零的样品．这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸Al作欧姆接触后,都在正向偏置下观察到电致发光（EL）．在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同．但掺Al结构的发光强度普遍比不掺Al结构强．另外,这两种结构的EL具体振荡特性有明显不同．对这两种结构的电致发光的物理机制和SiO2中掺Al的作用进行了分析和讨论．     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

HF chemical etching of SiO2 on 4H and 6H SiC

Thickness and etch rate of SiO₂ films thermally grown on hexagonal SiC substrates were compared to results obtained from SiO₂/Si samples. The data confirm that profilometry and ellipsometry yield the same thickness values for oxides grown on Si and SiC. Within the accuracy of our measurements, oxides grown on different polytypes and faces of SiC etch at the same rate in a HF acid solution. The etch rate using a 50:1 H₂O:HF(50%) solution at room temperature is 0.1 nm/s and is uniform throughout the thickness of the SiO₂ films. The rate is the same as that obtained for SiO₂ grown on Si.     

Optical characteristics of Si/SiO2 multilayers prepared by magnetron sputtering

Si/SiO₂ multilayers have been successfully prepared by magnetron sputtering and subsequently thermal annealed in an Ar atmosphere at a temperature of more than 500 °C. The surface of the as-deposited films is compact and smooth, and the distribution of grain size estimated to be 20 nm is uniform. For Si/SiO₂ multilayers annealed at 1100 °C, the Si sublayer sandwiched between potential barrier SiO₂ is crystalline structure by means of the analysis of Raman spectra and XRD data. The visible PL peak accompanying to a blue-shift with the decrease of Si sublayer thickness has been observed, and the intensity of this peak enhances with the increase of annealing temperature. The visible luminescence properties of Si/SiO₂ multilayers can be ascribed to quantum confinement of electron-hole pairs in quantum wells with grain size lower than 4.5 nm. In Si/SiO₂ multilayers, not only quantum confinement but also Si-SiO₂ interface states play an important role in the optical transition. The PL peak located at 779 nm is independent of the thickness of Si sublayer, so it may be ascribed to interface mediated transition. Typical Si dangling bonds defect could be a dominating obstacle to high luminescence efficiencies.     

Light emission from Si/SiO2 superlattices fabricated by RPECVD

Si/SiO₂ superlattices that exhibit intense luminescence properties were fabricated by remote plasma enhanced chemical vapor deposition. (RPECVD) and subsequent rapid thermal annealing for silicon crystallization. The effects of charge carrier confinement like blue shifting of the PL spectra and intensity increase with decreasing Silicon quantum well thickness are observed in low temperature photoluminescence experiments. The Si/SiO₂ interface quality is calculated from capacitance voltage (CV) measurements on metal oxide semiconductor teststructures showing excellent layer and Si/SiO₂ interface properties. The Si crystallization process is investigated and analyzed by Raman and transmission electron microscopy. Decreasing the Si quantum well thickness to 2 nm leads to light emission at room temperature.     

SOI planar photonic crystal fabrication: Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Dry plasma etching of sub-micron structures in a SiO₂/Si/SiO₂ layer system using Cr as a mask was performed in a fluorocarbon plasma. It was determined that the best anisotropy could be achieved in the most electropositive plasma. A gas composition yielding the desired SOI planar photonic crystal structures was optimized from the available process gases, Ar, He, O₂, SF₆, CF₄, c-C₄F₈, CHF₃, using DC bias data sets. Application of the c-C₄F₈/(noble gas) chemistry allowed fabrication of the desired SOI planar photonic crystal. The average etching rates for the pores and ridge waveguide regions were about 71 and 97 nm/min, respectively, while the average SiO₂/Si/SiO₂ to Cr etching selectivity for the ridge waveguide region was about 33:1 in case of the c-C₄F₈/90%Ar plasma with optimized parameters.     

Characterization of crystalline MOCVD SrTiO3 films on SiO2/Si(100)

SrTiO₃ thin films (STO), were deposited on Si(100) covered by 2 nm of SiO₂, at different temperatures from 450 °C to 850 °C using liquid injection MOCVD, the bimetallic precursor being Sr₂Ti₂(OiPr)₈(tmhd)₄. The STO films were analysed by XRD, FTIR, SIMS and TEM. An amorphous layer was observed between STO and SiO₂/Si. The nature and thickness of the interlayer were determined, as well as the most favourable conditions for a good quality crystalline STO film, and a reduced interlayer.     

Growth of CsLiB6O10 thin films on Si substrate by pulsed laser deposition using SiO2 and CaF2 as buffer layers

CsLiB₆O₁₀ (CLBO) thin films are grown on Si (100) and (111) substrates using lower index SiO₂ and CaF₂ as buffer layers by pulsed KrF (248 nm) excimer laser ablation of stoichiometric CLBO targets over a temperature range of 425 to 725°C. A CaF₂ buffer layer is grown on Si by laser ablation while SiO₂ is prepared by standard thermal oxidation. From extended x-ray analysis, it is determined that CaF₂ is growth with preferred orientation on Si (100) at temperatures lower than 525°C while on Si (111) substrate, CaF₂ is grown epitaxially over the temperature range; this agrees well with observed reflection high energy electron diffraction patterns. X-ray 2θ-scans indicate that crystalline CLBO are grown on SiO₂/Si and CaF₂/Si (100). Analysis of reflectance spectra from CLBO/SiO₂/Si yields the absorption edge at 182 nm. Surface roughness of the CaF₂ and CLBO/CaF₂/Si film are 19 and 15 nm, respectively. This relatively rough surface caused by the ablation of wide bandgap CaF₂ and CLBO limits the application of CLBO for waveguiding measurement.     

Study of nitrogen impact on VFB-EOT roll-off by varying interfacial SiO2 thickness

Flat band voltage (V_FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO₂/nitrided-HfSiO stacks. V_FB increases when SiO₂ interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO₂ interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO₂ interface through the SiO₂ layer in thinner SiO₂ device, and accumulates near Si/SiO₂ interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO₂ devices due to the higher interfacial trap density.The V_FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Transport and electroluminescence mechanism in Au/（Si/ SiO2）/P-Si film

Following the development of information technolo-gy,it has been a tendency to take the place of electronby photon as a carrier of information,since photons canmove thousands ti mes faster than electrons ,which cani mprove the rate of communication.Silico…     

Influence of oxidation temperature on the microstructure and electrical properties of Ta2O5 on Si

The effect of the oxidation temperature (673-873 K) on the microstructural and electrical properties of thermal Ta₂O₅ thin films on Si has been studied. Auger electron spectroscopy and X-ray photoelectron spectroscopy results revealed that the films are non-stoichiometric in the depth; an interfacial transition layer between tantalum oxide and Si substrate, containing presumably SiO₂ was detected. It has been found by X-ray diffraction that the amorphous state of Ta₂O₅ depends on both the oxidation temperature and the thickness of the films—the combination of high oxidation temperature (>823 K) and thickness smaller than 50 nm is critical for the appearance of a crystal phase. The Ta₂O₅ layers crystallize to the monoclinic phase and the temperature of the phase transition is between 773 and 823 K for the thinner layers (<50 nm) and very close to 873 K for the thicker ones. The electrical characterization (current/voltage; capacitance/voltage) reveals that the optimal oxidation temperature for achieving the highest dielectric constant (∼32) and the lowest leakage current (10⁻⁸ A/cm² at 1 MV/cm applied field) is 873 K. The results imply that the poor oxidation related defects are rather the dominant factor in the leakage current than the crystallization effects.     

Ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructure

Ultrathin HfO₂ gate dielectrics have been deposited on strain-compensated Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. X-ray diffraction spectra show the films to be polycrystalline having both monoclinic and tetragonal phases. The formation of an interfacial layer has been observed by high-resolution transmission electron microscopy. Secondary ion mass spectroscopy and Auger electron spectroscopy analyses show the formation of an amorphous Hf-silicate interfacial layer between the deposited oxide and SiGeC films. The average concentration of Ge at the interfacial layer is found to be 2–3 at%. The leakage current density of HfO₂ gate dielectrics is found to be several orders of magnitude lower than that reported for thermal SiO₂ with the same equivalent thickness.     

Effects of annealing conditions on the properties of tantalum oxide films on silicon substrates

The formation of a SiO₂ layer at the Ta₂O₅/Si interface is observed by annealing in dry O₂ or N₂ and the thickness of this layer increases with an increase in annealing temperature. Leakage current of thin (less than 40 nm thick) Ta₂O₅ films decreases as the annealing temperature increases when annealed in dry O₂ or N₂. The dielectric constant vs annealing temperature curve shows a maximum peak at 750 or 800° C resulting from the crystallization of Ta₂O₅. The effect is larger in thicker Ta₂O₅ films. But the dielectric constant decreases when annealed at higher temperature due to the formation and growth of a SiO₂ layer at the interface. The flat band voltage and gate voltage instability as a function of annealing temperature can be explained in terms of the growth of interfacial SiO₂. The electrical properties of Ta₂O₅ as a function of annealing conditions do not depend on the fabrication method of Ta₂O₅ but strongly depend on the thickness of Ta₂O₅ layer.     

Electroluminescence mechanisms in SiO x N y (Si) nanocomposite films

With a view to creating the Si LED, the mechanisms of electroluminescence (EL) in SiO_xN_y(Si) nanocomposite films with Si nanocrystals embedded in the SiO_xN_y matrix are studied experimentally and theoretically. The most important results are obtained from a Au/SiO_xN_ySi)/p-Si structure having a semitransparent electrode, the oxynitride film containing Si nanocrystals with a mean size of 3–5 nm and a concentration of ～10¹⁸ cm^?3; the measurements are made on a reverse-biased structure (substrate potential negative). Room-temperature EL is observed in the visible and IR ranges; the respective peaks are located at wavelengths of 600–700 and about 1200 nm. The study examines current-voltage characteristics of the structure and the dependence of integrated EL intensity on current, voltage, film thickness, the type of substrate conductivity, etc. The following conclusions are drawn from the experimental and theoretical results: The IR branch is mainly associated with carrier heating, avalanche ionization, and formation of light-emitting microplasmas near the substrate-film interface. The visible branch is linked to (i) hot-electron injection from the substrate into the film and (ii) impact excitation of luminescent centers at nanocrystal-matrix interfaces.     

Growth and electrical properties of the (Si/Ge)-on-insulator structures formed by ion implantation and subsequent hydrogen-assisted transfer

Systematic features of endotaxial growth of intermediate germanium layers at the bonding interface in the silicon-on-insulator structure consisting of buried SiO₂ layer implanted with Ge⁺ ions are studied in relation to the annealing temperature. On the basis of the results for high-resolution electron microscopy and thermodynamic analysis of the Si/Ge/SiO₂ system it is assumed that the endotaxial growth of the Ge layer occurs via formation of a melt due to enhanced segregation and accumulation of Ge at the Si/SiO₂ interface. Effect of germanium at the bonding interface on the Hall mobility of holes in silicon layers with nanometer-scale thickness is studied. It is found that the structures including the top silicon layer with the thickness 3–20 nm and incorporating germanium feature the hole mobility that exceeds by a factor of 2–3 the hole mobility in corresponding Ge-free silicon-on-insulator structures.     

Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO2 tunnel layer

Stacked HfAlO-SiO₂ tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO₂ tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO₂ tunnel layer. Owing to the thermally induced traps in HfAlO-SiO₂ films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO₂/Pd NCs/1.5 nm-HfAlO/3.5 nm-SiO₂/Si structure. A N₂ plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO₂.     

Interactions between ferroelectric BaTiO3 and Si

Ferroelectric BaTiO₃ thin films were deposited on single crystal Si substrates by radio-frequency magnetron sputtering. Bilayer structures of BaTiO₃ thin films, either amorphous on polycrystalline (A/P) or polycrystalline on microcrystalline (P/M), were utilized to reduce the leakage current and to enhance the dielectric constant of the films compared to single polycrystalline and amorphous layer structures, respectively. Relatively lower charge density, determined by the capacitance-voltage measurement on the capacitors with a configuration of Au/ BaTiO/p-Si/Al, was detected for the BaTiO₃ thin film with a structure of P/M. The current-voltage characteristics of the Al/SiO₂(~1.8 nm)/p-Si/Al diodes fabricated on the Si after removing BaTiO₃ layers gave direct evidence of the preservation of the Si surface crystal by using a P/M instead of a A/P structure. This was further confirmed by the Auger electron spectroscopy analysis on the samples.     

Thin RF sputtered and thermal Ta2O5 on Si for high density DRAM application

Tantalum pentoxide thin films on Si prepared by two conventional for modern microelectronics methods (RF sputtering of Ta in Ar + O₂ mixture and thermal oxidation of tantalum layer on Si) have been investigated with respect to their dielectric, structural and electric properties. It has been found that the formation of ultra thin SiO₂ film at the interface with Si, during fabrication implementing the methods used, is unavoidable as both, X-ray photoelectron spectroscopy and electrical measurements, have indicated. The initial films (as-deposited and as-grown) are not perfect and contain suboxides of tantalum and silicon which act as electrical active centers in the form of oxide charges and interface states. Conditions which guarantee obtaining high quality tantalum oxide with dielectric constant of 32–37 and leakage current density less than 10⁻⁷ A/cm² at 1.5 V applied voltage (Ta₂O₅ thickness equivalent to about 3.5 nm of SiO₂) have been established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAM application.