Characterization and Properties of Nickel Aluminide Nanocrystals in an Alumina Layer for Nonvolatile Memory Applications

Intermetallic nanocrystal memory devices with nickel aluminide nanocrystals in the electron-trapping layer and an alumina layer as the blocking layer were prepared on the surface of oxidized silicon substrates by sputter-coating of Ni and Al₂O₃ in sequence, followed by an annealing procedure. Several aluminide nanocrystal memory devices are reported. The effect of annealing at 900°C on the memory properties was investigated. Intermetallic nanocrystals were identified by high-resolution transmission electron microscopy and x-ray photoelectron spectroscopy as Ni₂Al₃ with sizes of 15–20 nm. The results showed that a sixfold increase (0.37 V to 2.34 V) in the memory window could be achieved after annealing for the optimal time of 3 min.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

A novel two-step method is employed,for the first time,to fabricate nonvolatile memory devices that have metal nanocrystals.First,size-averaged Au nanocrystals are synthesized chemically;second,they are assembled into memory devices by a spin-coating technique at room temperature.This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually.In addition,processes at room temperature prevent Au diffusion,which is a main concern for the application of...     

使用化学方法常温合成金纳米晶并通过旋涂工艺将其组装的存储特性可调型非易失性存储器

3C行业的不断发展,催生了对高密度、持久保存、快速擦写、鲁棒可靠性的非易失性存储器(如flash)的持续需求,促使我们在科研上不断地深入研究新材料、新工艺。在本文中,我们首次采用了区别于传统CMOS工艺的两步工艺方法来制作金属纳米晶非易失性存储器。这种方法,由于将金纳米晶的化学合成和后续组装分离开来,所以能够独立地调节纳米晶的尺寸和组装密度,而且可以很好地避免一直困扰的金属扩散问题。最终的形貌表征和电学测量结果,证实存在一个最优化的纳米晶密度--在这个最优化条件下,我们的存储器件,既有持久的保存时间,又有较大的存储窗口。而组装密度的可调,同时可以满足我们对于大的存储窗口/较长保存时间某一方面的偏好。这些实验结果,都很好地证明了我们两步工艺方法的可行性。     

Ruthenium oxide metal nanocrystal capacitors with high-κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high-κ HfO₂/Al₂O₃ dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO₂/HfO₂/ruthenium oxide (RuO_x)/Al₂O₃/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO_x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10¹²/cm² and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO₂ and RuO₃ elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of ΔV ≈ 12.2 V at a sweeping gate voltage of ±10 V and ΔV ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10¹³/cm², low charge loss of <7% (ΔV ≈ 4.2 V) after 1 × 10⁴ s of retention time are observed due to the formation of RuO_x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO_x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler-Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.     

The influence of irradiation and subsequent annealing on Si nanocrystals formed in SiO2 layers

Luminescent Si nanocrystals formed in SiO₂ layers were irradiated with electrons and He⁺ ions with energies of 400 and 25–130 keV, respectively. The effects of irradiation and subsequent annealing at 600–1000°C were studied by the methods of photoluminescence and electron microscopy. After irradiation with low doses (～1 displacement per nanocrystal), it was found that photoluminescence of nanocrystals was quenched but the number of them increased simultaneously. After irradiation with high doses (～10³ displacements per nanocrystal), amorphization was observed, which is not characteristic of bulk Si. The observed phenomena are explained in terms of the generation of point defects and their trapping by Si-SiO₂ interfaces. Photoluminescence of nanocrystals is recovered at annealing temperatures below 800°C; however, an annealing temperature of about 1000°C is required to crystallize the precipitates. An enhancement of photoluminescence observed after annealing is explained by the fact that the intensities of photoluminescence originated from initial nanocrystals and from nanocrystals formed as a result irradiation are summed.     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Metal nanocrystal memories-part II: electrical characteristics

This paper describes the electrical characteristics of the metal nanocrystal memory devices continued from the previous paper [see ibid., vol. 49, p. 1606-13, Sept. 2002]. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime have been investigated and compared with Si nanocrystal memory devices. With hot-carrier injection such as the programming mechanism, retention time up to 10⁶ s has been observed and 2-bit-per-cell storage capability has been demonstrated and analyzed. The concern of the possible metal contamination is also addressed by current-voltage (I-V) and capacitance-voltage (C-V) characterizations. The extracted inversion layer mobility and minority carrier lifetime suggest that the substrate is free from metal contamination with continuous operations     

Using different work function nanocrystal materials to improve the retention characteristics of nonvolatile memory devices

Recently, nanocrystal nonvolatile memory (NVM) devices have attracted great research interest. Taking into account the effect of work function to account for the better retention characteristics for nanocrystals with larger work function, utilizing different work functions Au, W and Si as floating gates is proposed and comparatively studied in this paper. It was found that Au nanocrystals have better retention characteristic than W and Si. The good retention characteristic of the Au nanocrystal device is due to the larger work function and it is difficult for electrons captured by Au nanocrystal to escape from them. So, the retention characteristic of the device can be improved by using larger work function nanocrystal materials.     

Ni纳米晶制备及其在MOS电容中存储特性研究

优化了Ni纳米晶的制备工艺参数,得到了分布均匀,形状为球形,平均尺寸5nm,密度2×1012/cm2的Ni纳米晶。在此基础上,制备了包含Ni纳米晶的MOS电容结构。利用高频电容-电压(C-V)和电导-电压(G-V)测试研究了其电学性能,证明该MOS电容结构的存储效应主要源于金属纳米晶的限制态。电容-时间(C-t)测试曲线呈指数衰减趋势,保留时间600s,具有较好的保留性能。     

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.     

Optical properties of <Emphasis Type="Italic">p–i–n</Emphasis> structures based on amorphous hydrogenated silicon with silicon nanocrystals formed via nanosecond laser annealing

Silicon nanocrystals are formed in the i layers of p–i–n structures based on a-Si:H using pulsed laser annealing. An excimer XeCl laser with a wavelength of 308 nm and a pulse duration of 15 ns is used. The laser fluence is varied from 100 (below the melting threshold) to 250 mJ/cm² (above the threshold). The nanocrystal sizes are estimated by analyzing Raman spectra using the phonon confinement model. The average is from 2.5 to 3.5 nm, depending on the laser-annealing parameters. Current–voltage measurements show that the fabricated p–i–n structures possess diode characteristics. An electroluminescence signal in the infrared (IR) range is detected for the p–i–n structures with Si nanocrystals; the peak position (0.9–1 eV) varies with the laser-annealing parameters. Radiative transitions are presumably related to the nanocrystal–amorphous-matrix interface states. The proposed approach can be used to produce light-emitting diodes on non-refractory substrates.     

Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

Optimization of Si NC/P3HT Hybrid Solar Cells

Silicon nanocrystals (Si NCs) are shown to be an electron acceptor in hybrid solar cells combining Si NCs with poly(3‐hexylthiophene) (P3HT). The effects of annealing and different metal electrodes on Si NC/P3HT hybrid solar cells are studied in this paper. After annealing at 150 °C, Si NC/P3HT solar cells exhibit power conversion efficiencies as high as 1.47%. The hole mobility in the P3HT phase extracted from space‐charge‐limited current measurements of hole‐only devices increases from 2.48 × 10^?10 to 1.11 × 10^?9 m² V^?1 s^?1 after annealing, resulting in better transport in the solar cells. A quenching of the open‐circuit voltage and short‐circuit current is observed when high work function metals are deposited as the cathode on Si NC/P3HT hybrid devices.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.     

Atomic-force-microscopy visualization of Si nanocrystals in SiO<Subscript>2</Subscript> thermal oxide using selective etching

The topography and local hardness of the etched surfaces of layers of SiO₂ thermal oxide that contained Si nanocrystals in its bulk were studied using atomic-force microscopy. The Si nanocrystals were obtained by implanting Si⁺ ions into the oxide with subsequent high-temperature annealing. It is shown that the use of selective etching that removes the oxide material makes it possible to reveal Si nanocrystals that appear in the profile of etched surfaces in the form of nanohillocks with a height of up to 2–3 nm. These values are in satisfactory agreement with the average radius of Si nanocrystals in the SiO₂ oxide layer. Independent confirmation of the Si-nanocrystal observation was obtained by comparing the topography of etched surfaces with the local-hardness maps obtained for the same surfaces; in these maps, the hillocks appear as sites at the surface with a reduced hardness. The phase precipitation of implanted Si is also observed in the form of extended flat clusters oriented in the oxide bulk parallel to the oxide surface. The suggested method for revealing the Si nanocrystals and clusters incorporated into the oxide provides a convenient way to study the specific features of nucleation growth and spinodal decomposition in the Si solid solution in the SiO₂ oxide.