绝缘层材料及结构对薄膜晶体管性能的影响

基于半导体仿真软件Silvaco TCAD对薄膜晶体管(TFT)进行器件仿真,并结合实验验证,重点分析不同绝缘层材料及结构对TFT器件性能的影响。仿真及实验所用薄膜晶体管为底栅电极结构,沟道层采用非晶IGZO材料,绝缘层采用SiN_x和HfO_2多种不同组合的叠层结构。仿真及实验结果表明:含有高k材料的栅绝缘层叠层结构较单一SiN_x绝缘层结构的TFT性能更优;对SiN_x/HfO_2/SiN_x栅绝缘层叠层结构TFT,HfO_2取40nm较为合适;对含有高k材料的3层和5层绝缘层叠层结构TFT,各叠层厚度相同的对称结构TFT性能最优。本文通过仿真获得了TFT性能较优的器件结构参数,对实际制备TFT器件具有指导作用。     

Laterally Coupled DFB Lasers With Self-Aligned Metal Surface Grating by Holographic Lithography

A laterally coupled InGaAsP-InP distributed-feedback (DFB) laser operating around 1.55 mum was fabricated through a novel technique for the formation of metal surface gratings by holographic lithography. The self-aligned Cr DFB gratings were formed on the sidewalls as well as on both sides of the laser ridge by means of angled e-beam evaporation of Ti mask and metal-SiO₂ lift-off on the top of ridges. For an uncoated 3-mum-wide and 300-mum-long cavity, the device emitted an output power of ~9.7 mW/facet at an injection current of 100 mA with a threshold current of 29 mA and a slope efficiency of 0.14 mW/mA per facet at 20 degC under continuous-wave mode. A stable single-mode emission near 1.54 mum with a sidemode suppression ratio of nearly 28 dB was observed and a tuning coefficient of 0.21 nm/K was obtained in the temperature range of 15 degC -55 degC.     

1.5 μm wavelength distributed reflector lasers with verticalgrating

A 1.5 μm wavelength distributed reflector laser, consisting of a distributed Bragg reflector rear facet and a distributed feedback region, was realised using deep-etching technology. A low threshold current of I_th=12.4 mA and a high differential quantum efficiency of η_d=42% from the front facet was achieved with a submode suppression ratio of 33 dB (I=2.4 I_th) for a fifth-order grating, 220 μm long and 6 μm wide device at room temperature     

Bphen掺杂Cs_2CO_3作为电子传输层对OLED器件性能的影响

为改善OLED器件的载子注入平衡,本文在其结构ITO/MoO3/NPB/Alq3/Cs2CO3/Al中,分别引入高电子迁移率材料Bphen及Bphen∶Cs2CO3作为电子传输层。通过改变Bphen的厚度以及Bphen中Cs2CO3的体积掺杂浓度,研究其对器件发光亮度、电流密度和效率等性能的影响。实验结果表明,采用Bphen或者Bphen∶Cs2CO3作为电子传输层,均能提高器件的电子注入能力,改善器件的性能。相比于未引入Bphen的器件,采用25nm的Bphen作为电子传输层,改善了器件的电子注入,使器件的最大电流效率提高112%;采用体积掺杂浓度为15%,厚度为5nm的Bphen∶Cs2CO3作为电子传输层,减小了电子注入势垒,使器件的最大电流效率提高27%,并且掺杂层厚度的改变对器件的电子注入影响很小。该方法可用于OLED器件的阴极修饰,对器件性能的提升将起到一定的促进作用。     

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO₂ gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO_x, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN_x, gate dielectrics.     

Effects of high-injection barrier (HIB) position on bipolartransistor characteristics

This paper analyzes the effects of the vertical position over the n^$collector of the n-type layer formed by a high energy phosphorus implantation on the high current level characteristics of the n-p-n bipolar device. From the device simulation and measurement data, we demonstrate that the barrier located near the buried layer plays a more effective role in the suppression of both the base-widening effect and the avalanche multiplication effect in the high collector current region, whereas the barrier near the intrinsic base achieves base Gummel number reduction and high-current gain at a low collector current level. This paper is also concerned with a quasi-saturation phenomenon found in devices in which the barrier is near the base-collector junction. The factor accounting for this phenomenon is analyzed by way of two-dimensional simulations and measurements     

0.15-$muhboxm$-Gate InAlAs/InGaAs/InP E-HEMTs Utilizing Ir/Ti/Pt/Au Gate Structure

High-current 0.15-mum-gate enhancement-mode high-electron mobility transistors utilizing Ir/Ti/Pt/Au gate metallization were fabricated using a new process including a high-temperature gate anneal that is required for Schottky-barrier height enhancement for the Ir-based gate contact. SiN_x encapsulation was employed to prevent thermal degradation of device layer during the high-temperature gate anneal. Excellent enhancement-mode operation, with a threshold voltage of 0.1 V and I_DSS of 2.1 mA/mm, was realized. Both the annealed and unannealed devices exhibited high g_m,max and I_D,max of 800 mS/mm and 430 mA/mm, respectively. A unity current-gain cutoff frequency f_T of 151 GHz and a maximum oscillation frequency f_MAX of 172 GHz were achieved. From the dc and RF characteristics, it can be deduced that there was no degradation of the gate contact and the heterostructure due to gate annealing. Furthermore, it was found that the gate diffusion during gate annealing was negligible since no increase in g_m,max was observed     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Manufacturable Processes for $leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Manufacturable processes to reduce both channel and external resistances (R_Ext) in CMOS devices are described. Simulations show that R_Ext will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiN_x liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug resistance (R_c) is reduced by 40% by optimizing preclean, liner/barrier, and nucleation steps. Replacing the fill material with Cu reduces R_c by > 35% as compared to W. The Schottky barrier height of silicide contacts to p-Si is reduced by 0.12 eV with a 10% addition of Pt, resulting in a ~10% increase in the PMOS drive current. By implementing a two-step anneal process (spike + laser), the source/drain-extension resistance can be reduced by 20%.     

Very low threshold current density room temperature continuous-wavelasing from a single-layer InAs quantum-dot laser

Continuous-wave (CW) lasing operation with a very low threshold current density (J_th=32.5 A/cm²) has been achieved at room temperature by a ridge waveguide quantum-dot (QD) laser containing a single InAs QD layer embedded within a strained InGaAs quantum well (dot-in-well, or DWELL structure). Lasing proceeds via the QD ground state with an emission wavelength of 1.25 μm when the cavity length is longer than 4.2 mm. For a 5-mm long QD laser, CW lasing has been achieved at temperatures as high as 40°C, with a characteristic temperature T₀ of 41 K near room temperature. Lasers with a 20 μm stripe width have a differential slope efficiency of 32% and peak output power of >10 mW per facet (uncoated)     

Observation of degradation recovery in 1.3-μm GaInAsP-InPinverted-rib semiconductor lasers

This paper reports some effects arising from interrupted lifetest of 1.3-μm GaInAsP-InP inverted-rib laser diodes. This unconventional lifetest method involves constant power biasing at 4 mW/facet and 8 mW/facet, respectively, at 50°C, followed by a period during which the devices were left unbiased at room temperature (off-test period). At the end of the off-test period, the devices were put back on constant power biasing at 50°C. A pronounced reduction in the threshold current, current for 4 mW/facet and 8 mW/facet were observed during the initial part of the off-test period. Similar improvements were also seen in the external quantum efficiency with corresponding variations also occurring in the device series resistance, characteristic temperature, threshold junction voltage, and the emission spectra linewidth. Such recovery effects have so far been observed to occur only in the GaInAsP-InP inverted-rib devices     

1.55-/spl mu/m DFB lasers utilizing an automatically buried absorptive InAsP layer having a high single-mode yield

We describe 1.55-/spl mu/m distributed feedback laser diodes (DFB LDs) having a single-mode (SM) yield as high as 80% and 93% for as-cleaved and antireflection/high reflection (AR/HR=3%/95%) coated devices, respectively. The high SM yield was achieved by introducing an automatically buried InAsP layer between a concave of InP corrugations and an overgrown layer. The use of the automatically buried InAsP layer implemented by a single step growth makes the device fabrication process much easier than that of conventional loss-coupled DFB LDs. Fabricated DFB LDs with AR/HR-coated facets showed a low threshold current of 8 mA (34 mA) and a high slope efficiency of 0.32 mW/mA (0.22 mW/mA) at 25/spl deg/C (85/spl deg/C). A sidemode suppression ratio better than 40 dB was obtained for the temperature range between -20/spl deg/C and 85/spl deg/C and the injection current range between 20 and 100 mA.     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Device analysis for a-Si:H thin-film transistors with organicpassivation layer

Two dimensional device analysis has been performed to explain the experimental drain current-gate voltage (I_D-V_GS) characteristics of hydrogenated amorphous silicon thin-film transistors with various passivation layers. The shift of the I_D-V_GS curve in the negative direction and the increase of S-factor (the inverse of subthreshold slope in logarithmic I_D-V_GS curve) can be explained well by introducing positive fixed charges and defect states in the back interface region. It was found that the positive fixed charge and the defect density of a-Si:H TFT with an organic passivation layer are higher than those of conventional a-Si:H TFT with a silicon-nitride (SiN_x) passivation layer. The simulation shows that the front and back interfaces interact and this explains why the passivation affects the device performance such as V_th and S-factor in a-Si:H TFTs     

非故意掺杂吸收层InP/InGaAs异质结探测器研究

为了获得低噪声铟镓砷（InGaAs）焦平面,需要采用高质量的非故意掺杂InGaAs（u-InGaAs）吸收层进行探测器的制备。采用闭管扩散方式,实现了Zn元素在u-InGaAs吸收层晶格匹配InP/In_0.53Ga_0.47As异质结构材料中的P型掺杂,利用扫描电容显微技术(SCM)对Zn在材料中的扩散过程进行了研究,结果表明,随着扩散温度和时间增加,p-n结结深显著增加,u-InGaAs吸收层材料的扩散界面相比较高吸收层浓度材料（5×1016 cm?3）趋于缓变。根据实验结果计算了530 ℃下Zn在InP中的扩散系数为1.27×10?12 cm2/s。采用微波光电导衰退法(μ-PCD)提取了InGaAs吸收层的少子寿命为5.2 μs。采用激光诱导电流技术(LBIC)研究了室温下u-InGaAs吸收层器件的光响应分布,结果表明:有效光敏面积显著增大,对实验数据的拟合求出了少子扩散长度L_D为63 μm,与理论计算基本一致。采用u-InGaAs吸收层研制的器件在室温(296 K)下暗电流密度为7.9 nA/cm2,变温测试得到激活能E_a为0.66 eV,通过拟合器件的暗电流成分,得到器件的吸收层少子寿命τ_p约为5.11 μs,与微波光电导衰退法测得的少子寿命基本一致。     

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm⁻² and a collector bias, V_CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

The injection efficiency controlled IGBT

An IGBT structure in which the anode injection efficiency changes with current density, the injection efficiency controlled IGBT (EEC-IGBT), is proposed. The anode injection efficiency of the IEC-IGBT is controlled via a current sensor inherent in its structure. Anode injection efficiency is strongly enhanced at low device current density and significantly reduced at high device current density. This enables the device to have a low on-state voltage drop (V_on) and superior safe operation area (SOA), making it very suitable for high-power applications. Simulation results based on 3.3 KV DMOS NPT devices indicate the on-state voltage drop of the IEC-IGBT is reduced by 0.6 V (20%) and the short-circuit SOA (SCSOA) is improved by several times compared to the conventional IGBT     

Suppression of gate leakage current in n-AlGaAs/GaAs power HEMTs

Experiments of gate leakage current in a double-channel n-AlGaAs/GaAs FET with SiN_x film passivation indicated that the gate leakage current and its stability depend critically on the stoichiometry of the surface. The content of NH₄ OH in the etching solution prior to the SiN_x film deposition and the NH ₃/SiH₄ gas content ratio, particularly at the initial stage of plasma-CVD SiN, deposition, should be selected to minimize the surface state density of possible antisite defects. Extremely low gate leakage currents of 50 nA/mm have been obtained with an improved process, which is useful to realize low-distortion FETs