Experimental Comparison Between Sub-0.1-μm Ultrathin SOI Single- and Double-Gate MOSFETs: Performance and Mobility

This paper presents an experimental comparison between single-gate (SG) and double-gate (DG) transistors performance. Using a novel process flow, we managed to cointegrate these two devices on the same wafer with a TiN metal gate. Short-channel effect control, static performance, and mobility are quantified for each architecture. An in-depth mobility study is performed for a wide range of temperatures (10 K-300 K) and gate lengths (10-20 nm) while channel thickness is fixed at 6 nm. This study experimentally highlights the advantages of DG devices over SG transistors. Good mobility values are obtained for both architectures and we show the advantages of ultrathin body devices over bulk transistors. Finally, we demonstrate that Coulomb scattering is the primary cause of the mobility degradation in short-channel devices     

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.     

Sub-10-nm wide trench, line, and hole fabrication using pressed self-perfection

We report a new approach to adjust and improve nanostructures after their initial fabrication, which can reduce the trench width and hole diameter to sub-10 nm, while smoothing edge roughness and perfecting pattern shapes. In this method, termed pressed self-perfection by liquefaction (P-SPEL), a flat guiding plate is pressed on top of the structures (which are soften or molten transiently) on a substrate to reduce their height and guide the flow of the materials into the desired geometry before hardening. P-SPEL results in smaller spacing between two structures or smaller holes in a thin film.     

Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail.     

Breakdown of universal mobility curves in sub-100-nm MOSFETs

We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model. Owing to the high efficiency of the transport kernel, effective mobility in 3-D MOSFETs with realistic Si-SiO/sub 2/ interfaces reconstructed from a Gaussian or exponential correlation function can be simulated in a statistical manner. We first demonstrate a practical calibration procedure for the interface mobility and affirm the universal behavior in the long channel limit. Next, effective mobility in ensembles of MOSFETs with a gate length down to 10 nm is investigated. It is found that the random-discrete nature of the Si-SiO/sub 2/ interface leads to a distribution of carrier mobility below the interface, which can deviate considerably from universal mobility curves when L/sub gate/<6/spl Lambda/, where /spl Lambda/ is the correlation length for the SiO/sub 2/ interface.     

A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate SOI MOSFETs

This paper provides a comparative study of carrier transport characteristics for multiple-gate silicon-on-insulator MOSFETs with and without the nonoverlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the nonoverlapped devices, however, we found insensitive temperature dependence for drain current in both subthreshold and inversion regimes. Our low-temperature measurements indicate that the intersubband scattering is the dominant carrier transport mechanism for narrow overlapped multigate field-effect transistors(MuGFETs). For the nonoverlapped MuGFETs, the voltage-controlled potential barriers in the nonoverlapped regions may give rise to the weak localization effect (conductance reduction) and the quantum interference fluctuations.     

A New Method to Extract Carrier Velocity in Sub-0.1-$mu$m MOSFETs Using RF Measurements

A novel RF method based on the accurate extraction of the gate–source channel capacitance and intrinsic transconductance from measured$S$-parameters is proposed to determine the effective carrier velocity of sub-0.1-$mu$m MOSFETs in the velocity saturation region. This method is developed to avoid the errors associated with underestimated charge in traditional ones. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed along with the linear dependence of measured electron velocity on$1/L_ poly$in bulk N-MOSFETs with a channel length of less than 0.085$mu$m. This extracted result is more accurate than that of previous methods, because$v_ eff$is directly determined from the gate–source channel capacitance at high V$ ds$instead of that at V$ ds=0$.     

Sub-10 nm structures on silicon by thermal dewetting of platinum

A study of the dewetting behavior of platinum-thin-films on silicon was carried out to determine how variation of dewetting parameters affects the evolution of film morphology and to pinpoint which parameters yielded the smallest, most circular features. Platinum film thickness as well as dewetting time and temperature were varied and the film morphology characterized by means of scanning electron microscopy (SEM) analysis. Two different pathways of dewetting predicted in the literature (Vrij 1966 Discuss. Faraday Soc. 42 23, Becker et al 2003 Nat. Mater. 2 59-63) were observed. Depending on the initial criteria, restructuring of the film occurred via hole or droplet formation. With increased annealing time, a transition from an intermediate network structure to separated islands occurred. In addition, the formation of multilayered films, silicide crystals and nanowires occurred for certain parameters. Nevertheless, the dewetting behavior witnessed could be related to physical processes. Droplets with a mean diameter of 9 nm were formed by using a 1.5 nm thick platinum film annealed at 800?°C for 30 s. To demonstrate the suitability of the annealed films for further processing, we then used the dewetted films as masks for reactive ion etching to transfer the pattern into the silicon substrate, forming tapered nanopillars.     

A Computational Study of Dopant-Segregated Schottky Barrier MOSFETs

A dopant-segregated Schottky barrier MOSFET is simulated by Monte Carlo method in this paper. The feature that dopant-segregated structure can improve on-current is revealed. The influence of dopant-segregated structure parameters on device performance is investigated, and the guideline for device design optimization is that the dopant-segregated region should overlay the whole Schottky barrier region. Some carrier transport details are also demonstrated here. The maximal velocities at source and drain sides all decrease with the increase of dopant-segregated region length. The maximal velocity at source side shows saturation with the existence of dopant-segregated structure when drain voltage increases while the maximal velocity at drain side shows no saturation.      

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

A Sub-10 nm Vertical Organic/Inorganic Hybrid Transistor for Pain-Perceptual and Sensitization-Regulated Nociceptor Emulation

Pain-perceptual nociceptors (PPN) are essential sensory neurons that recognize harmful stimuli and can empower the human body to react appropriately and perceive precisely unusual or dangerous conditions in the real world. Furthermore, the sensitization-regulated nociceptors (SRN) can greatly assist pain-sensitive human to reduce pain sensation by normalizing hyperexcitable central neural activity. Therefore, the implementation of PPNs and SRNs in hardware using emerging nanoscale devices can greatly improve the efficiency of bionic medical machines by giving them different sensitivities to external stimuli according to different purposes. However, current most-normal organic/oxide transistors face a great challenge due to channel scaling, especially in the sub-10 nm channel technology. Here, a sub-10 nm indium-tin-oxide transistor with an ultrashort vertical channel as low as ≈3 nm, using sodium alginate bio-polymer electrolyte as gate dielectric, is demonstrated. This device can emulate important characteristics of PPN such as pain threshold, memory of prior injury, and pain sensitization/desensitization. Furthermore, the most intriguing character of SRN can be achieved by tuning the channel thickness. The proposed device can open new avenues for the fascinating applications of next-generation neuromorphic brain-like systems, such as bio-inspired electronic skins and humanoid robots.     

阴极射线管显示器不同屏显字符形状和颜色特征的识别工效的比较研究

本实验研究用数字、汉字、飞机图标和几何图形比较了颜色编码、形状编码及颜色和形状双重编码的检测工效。在阴极射线管（ＣＲＴ）显示器屏幕的９个固定位置（３×３矩阵）上同时显示同一形状不同颜色、同一颜色不同形状或颜色和形状都不相同的３、６或９个字符，让被试按颜色、形状或同时按颜色和形状找出一目标字符，并按压键标数字与所找字符显示位置号相同的键。每个字符在各个位置的显示概率是相等的，显示的先后次序是随机的。字符的显示、目标字符的检测时间和错误率由计算机系统程序控制，实时计算和打印记录。结果表明，就检测工效而言，颜色编码优于颜色和形状双重编码，后者又优于形状编码；目标字符的检测时间随同时显示字符的数量的增加而增长，并得到了从同时显示的３、６、９个字符中按不同特征检测目标字符的搜索一识别时间和包括按键操作在内的目标检测时间。     

国内外食品接触金属烹饪器具不粘性能要求对比分析研究

本文介绍了法国、美国、英国以及我国食品接触金属烹饪器具不粘性能标准现状,分析了我国与法国、美国、英国不粘性能要求存在的差异,并提出了完善我国金属烹饪器具不粘性标准的建议.     

A Novel Spacer Process for Sub-10-nm-Thick Vertical MOS and Its Integration With Planar MOS Device

We demonstrate vertical capacitors using a novel spacer process capable of fin thickness down to 5 nm. We also integrate this process compatibly with planar devices on the same die using minimal additional mask steps. Various implant conditions, order of implant step, and starting substrate dopings are studied and best conditions identified through TSUPREM4 simulations and later through experiments to ensure process robustness and dopant tunability for the vertical devices as well as to ensure comparable performance for planar and vertical devices. In anticipation of usage of this process in a high-density environment, the impact of isolation density on the leakage characteristics of vertical capacitors is also studied. After simultaneously fabricating planar and vertical structures, electrical characterization using capacitance–voltage (C–V) and current–voltage (I–V) measurements is performed. Functional capacitors for both types of devices are obtained. Oxide thickness is backtracked using I–V, C–V, and TEM and yield consistent results. The leakage current shows expected trends with voltage and is successfully fitted using prevalent tunneling models. The vertical structures are found to suffer from two problems: a larger leakage current and an additional planar parasitic capacitance due to a finite polysilicon gate thickness. The larger leakage is attributed to thin corners as confirmed by higher leakage in structures having a larger fraction of corner area (higher isolation density structures). A modified novel vertical device process circumventing both these problems by yielding thicker bottom and corner oxides is proposed and experimentally demonstrated. Finally, a path to extending this process for vertical transistor fabrication is shown in simulations.     

动态联盟实例比较研究

通过比较分析动态联盟实例,探讨了成功的动态联盟具有的８个特征：明确的目标,竞争对手的有效界定,核心成员彼此互补的核心优势,组织保证,资金保证,各个成员间合理的组织结构,供应链的支持作用及善始善终。     

Assemblies of carbon nanotubes and unencapsulated sub-10-nm gold nanoparticles

The development of assemblies consisting of unencapsulated, sub-10-nm gold particles attached to individual carbon nanotubes (CNTs) with diameters of 2 nm is described. The assemblies are formed on the surface of a porous anodic alumina (PAA) template on which the CNTs (single- or double-walled) are grown by plasma-enhanced chemical vapor deposition. The Au nanoparticles are formed through an indirect evaporation technique using a silicon nitride membrane mask, and diffuse along the PAA surface into the regions containing CNTs. The nanoparticles bind relatively strongly to the CNTs, as indicated by observations of nanoparticles that are suspended over pores or that move along with the CNTs. This approach may provide a new method to functionalize CNTs for chemical or biological sensing and fundamental studies of nanoscale contacts to CNTs.     

有关AMBN热分解特征的研究

该文用蓄热贮存试验法测定了自反应性物质ＡＭＢＮ试样从试样进入恒温箱到发生热爆炸过程中温温度（Ｔ）随时间（ｔ）的变化曲线；描述和解释了Ｔ－ｔ曲线的变化特点和ＡＭＢＮ试样的热分解、熔解及熔点下降之间的关系，并指出当ＡＭＢＮ试样受热后呈固－液两相共存和熔点下降时，预示着试样将发生自加速反应。