A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.     

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

A 50-mW/ch 2.5-gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking

Typical frequency doublers achieve high conversion gain by reflecting back the 2nd harmonic to the input port of the active device through a quarter-wave open-circuited stub. In this paper, a S-band frequency doubler with a 12 dB conversion gain outperforms the conventional design by 5 dB, after replacing the conventional stub with a Compact Microstrip Resonant Cell (CMRC). The CMRC serves as suitable terminations for both the 2nd and 3rd harmonics to enhance the desired output power of the 2nd harmonic, while appearing as a good pass-band for the fundamental frequency.     

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μmSOI-CMOS technology

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers     

A 27-mW CMOS fractional-N synthesizer using digital compensationfor 2.5-Mb/s GFSK modulation

A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-μm CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH Σ-Δ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard     

A 1.25-gb/s burst-mode receiver for GPON applications

This paper presents a 1.25-Gb/s burst-mode receiver (BMRx) for upstream transmission over gigabit passive optical networks (G-PONs). The dc-coupled receiver uses a unique arrangement of three limiting amplifiers to convert the bursty input signal to a current mode logic output signal while rejecting the dc offset from a preceding transimpedance amplifier. Peak detectors extract a decision threshold from a sequence of 12 successive nonreturn-to-zero (NRZ) 1's and 12 successive NRZ 0's received at the beginning of each packet. Automatic compensation of the remaining offsets of the BMRx is performed digitally via digital-to-analog converters. The chip was designed in a 0.35-/spl mu/m SiGe BiCMOS process. The receiver contains an APD with a gain of 6 and a transimpedance amplifier and shows a sensitivity of -32.8 dBm and a dynamic range of 23.8 dB. A sensitivity penalty of 2.2 dB is incurred when a packet with average optical power of -9 dBm precedes the packet under consideration, the guard time between the packets being 25.6 ns. The BMRx includes activity detection circuitry, capable of quickly detecting average optical levels as low as -35.5 dBm. The performed measurements prove that the receiver meets the G-PON physical media dependent layer specification defined in ITU-T Recommendation G.984.2.     

A CMOS 10-gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multilevel pulse amplitude modulation (PAM) transmitter is proposed. A data-look-ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. This technique also eliminates the need for a pre-driver block, which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18-/spl mu/m standard digital CMOS technology. The transmitter achieves 3.5 GS/s (7 Gb/s) with a 1.7-V supply and 5 GS/s (10 Gb/s) with a 2-V supply and it occupies an area of 0.16 mm/sup 2/. The output driver and the entire transmitter consume only 11.25 and 66 mW at 7 Gb/s (20 and 121 mW at 10 Gb/s), respectively, which are the lowest reported powers at this speed.     

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS

A divide-by-16.5 frequency divider, providing read- and write-clocks for an elastic buffer or a gearbox between 10.3125-Gb/s and quad 3.125-Gb/s transceivers in 10-G Ethernet application, is presented. The high-speed and noninteger division is designed by cascading high-speed divide-by-3 followed by divide-by-5.5 which uses double-edge-triggered flip-flops. The divide-by-3 circuit receives and generates 5.15625-GHz and 1.71875-GHz differential clocks with a 50% duty cycle, respectively. Based on current-mode logics (CMLs), the proposed divide-by-16.5 scheme is implemented in a 0.13-/spl mu/m CMOS technology to achieve over 5-GHz operation while consuming 18 mW from a 1.2-V supply.     

A 384-kbit/s ISDN burst transceiver

An Integrated Services Digital Network (ISDN) burst transceiver circuit is described which provides two-wire data transmission using the time-compression multiplexing technique and an AMI (alternate mark inversion) line code at a line bit rate of 384 kb/s. An automatic line equalizer handles a wide variety of twisted pair cable types including highly capacitive cables with up to 32-dB insertion loss at the Nyquist frequency.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

A 3.5-mW, 2.5-GHz diversity receiver and a 1.2-mW, 3.6-GHz VCO insilicon on anything

In this paper, first results of radio-frequency (RF) circuits processed in a novel silicon bipolar technology called silicon on anything (SOA) are presented. This technology was developed with the application of low-power, high-frequency circuits in mind. Three test ICs are discussed: a fully integrated 3.6-GHz voltage-controlled oscillator, a fully integrated 2.5-GHz diversity receiver front end, and an intermediate-frequency IC containing channel selectivity and demodulation circuits. Measurement results show that using this technology, significant power savings are possible for RF circuits     

A 2.5-Gb/s 15-mW clock recovery circuit

This paper describes the design of a 2.5-Gb/s 15-mW clock recovery circuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation. In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions. Fabricated in a 20-GHz 1-μm BiCMOS technology, the circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz     

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

100-gb/s transmission using orthogonal frequency-division multiplexing

The possibility of 100-Gb/s transmission over 25-GHz bandwidth using orthogonal frequency-division multiplexing (OFDM) is demonstrated. It is shown that 100-Gb/s transmission over 3840 km can be achieved using single-sideband quadrature-phase-shift keying OFDM transmission and low-density parity-check codes.     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.     

Serial dark soliton for 100-gb/s applications

We analyze the performance through numerical simulations of a new modulation format: serial dark soliton (SDS) for wide-area 100-Gb/s applications. We compare the performance of the SDS with conventional dark soliton, amplitude-modulation phase-shift keying (also known as duobinary), nonreturn-to-zero, and return-to-zero modulation formats, when subjected to typical wide-area-network impairments. We show that the SDS has a strong chromatic dispersion and polarization-mode-dispersion tolerance, while maintaining a compact spectrum suitable for strong filtering requirement in ultradense wavelength-division-multiplexing applications. The SDS can be generated using commercially available components for 40-Gb/s applications and is cost efficient when compared with other 100-Gb/s electrical-time-division-multiplexing systems.     

Modeling O/E characteristics of 40-gb/s InGaAs side-illuminated waveguide photodiode submodule for optical receivers

In this paper, the circuit models of a waveguide photodiode (WGPD) and its submodule were investigated, and the O/E characteristics of a WGPD submodule are examined. Test structures of the WGPD and WGPD submodule were fabricated and microwave return loss (S11) was measured and compared with simulated data to validate the circuit models. With the established submodule model, optical to electrical (O/E) characteristics were measured and compared with the modeled data to analyze the effects of model parameters on the submodule performance. Based on the results, it can be concluded that the suggested submodule model can explain the characteristics of the submodule performance. In addition, parasitic components that originated from the ribbon bonding block can crucially impact on the performance of WGPD submodule.     

Monolithically integrated 40-gb/s switchable wavelength converter

An all-optical switchable wavelength-converting module at 40 Gb/s line rate is demonstrated in a fully integrated InP chip. The device combines a semiconductor optical amplifier-based wavelength converter and a fast-tunable multifrequency laser. Sub-nanosecond switching among the eight channels of the integrated laser is shown, and error-free operation of the wavelength conversion process at 40 Gb/s for each wavelength is demonstrated. The applications of fast switching wavelength conversion for optical switching and packet routing are discussed.