基于Kintex-7 FPGA的DDR3 SDRAM接口应用研究

针对FPGA中使用DDR3进行大容量数据的缓存应用背景,采用模块化设计方法,提出基于Xilinx Kintex-7 FPGA的DDR3 SDRAM FIFO接口设计方案。在分析DDR3用户接口特点和用户接口时序的基础上,对不同读/写模式进行效率测试。借鉴标准FIFO的设计思想,结合DDR3 SDRAM控制器的特点,设计遍历状态机对该FIFO接口进行读/写测试。最后,原型机平台验证了该接口不仅具有标准FIFO简单易用的功能,而且具有存储空间大等优势。     

高效可配置浮点FFT处理器设计

为了克服高精度浮点FFT处理器具有较大资源开销的设计瓶颈,采用基于单口存储器的FIFO构建共享蝶形结构的R2/22SDF流水可配置结构.采用适合浮点设计的基2/22算法实现流水结构,不仅有利于可配置电路的实现,还能够有效减少复数乘法次数,提高复数乘法器的计算效率.采用双倍数据位宽的单口存储器实现FIFO存储器,有效避免了双口存储器面积和功耗较大的问题.改进的蝶形共享结构实现两级蝶形的合并,解决了单路径延迟反馈流水线结构蝶形单元利用率低的问题.与传统流水线结构FFT处理器设计相比,有效降低了浮点设计中的资源开销,提高了计算单元的利用效率.     

一种基于PCI Express总线的DMA高速传输系统

介绍了DMA高速传输系统的结构以及DMA的设计,搭建了×8通道的PCIE系统.在整个系统的板卡终端,连接了两个FIFO,提供标准的FIFO接口,能连接光纤数据、CT图像采集数据、A/D采样数据等.实验验证了DMA读和DMA写两种传输方式的可靠性,测试了DMA读写的传输速度.实验表明,在单次DMA传输大小达到1MB时,×8通道的PCIE系统DMA读和写速度均能达到1 000 MB/s,可满足大部分高速数据传输的要求.     

基于EDA技术的高速FIFO设计

利用Lattice公司的在系统可编程逻辑器件ispLSI6192芯片构造4个双向、独立的128×9位F IFO高速数据存储栈区(FIFO),并对芯片可编程逻辑编程建立快速地址加1计数器以及FIFO控制逻辑,控制逻辑分别对4个FIFO栈区进行读/写控制;实现将系统的高速数据栈区及其控制逻辑功能在同一个芯片上实现,从而提高计算机数据通信的速度、效率以及提高系统的集成度和降低系统的故障率。     

基于低功耗ASIP的循环缓存的设计

针对ASIP处理器的低功耗设计要求,提出了多段式的循环缓存结构.该结构与原有的循环缓存结构相比,提高了缓存存储器的利用率.本设计通过减少对主存储器的读操作和缓存存储器的写操作的方式来降低程序存储器的功耗.在SMIC的0.13μm工艺条件下,将该结构应用于助听器处理器中,并进行功耗验证.分析表明,该方法以较小的面积开销,最高可将存储器的功耗降低大约50%,有效的降低程序存储器的功耗.     

基于Verilog HDL语言的32X8 FIFO设计

介绍了FIFO的基本概念、设计方法和步骤，采用了一种新颖的读、写地址寄存器和双体存储器的交替读、写机制，实现了FIFO的基本功能，同时使本32X8 FIFO拥有可同时读、写的能力。完全基于Verilog HDL语言实现了电路功能并应用Synopsys公司的Design Compiler和VCS对其进行综合、仿真。     

一类基于AMBA总线的SDRAM控制器设计

提出一类SDRAM控制器的设计方法,针对SDR SDRAM的突发特性,采用数据预读取机制提高SDRAM的读取效率,同时又加入了写指令FIFO消除读缓存带来的负面影响.并且以该控制器在AHB总线的集成为例,实现了控制器在SoC中的应用.功能仿真和FPGA验证均表明本设计能够准确高效地实现对SDR SDRAM的访问控制.     

一种延迟可控的异步FIFO电路设计

基于传统异步FIFO延迟电路设计了 一种延迟可控的异步FIFO电路.该电路在实现数据跨时钟域传输的同时增加了延迟控制模块,通过调节读指针与写指针的差值实现整数延迟的控制,通过调节读时钟与写时钟的相位差实现高精度的小数延迟控制.建立VCS验证平台,进行功能验证.结果表明,该FIFO电路实现了数据跨时钟域传输和延迟动态控制...     

USB设备控制器端点缓冲区的优化设计

讨论使用异步FIFO作为USB端点缓冲区的设计方案.根据USB四种传输类型的特点,灵活地设计了不同端点缓冲区的实现方案.特别是针对控制端点传输的特殊性,提出一种新型的双向FIFO设计.与传统结构相比,该方案在保证控制传输的功能下电路的实现面积减小了近1/2.对于其他类型端点的设计方案,为了保证传输速度,使用了双缓冲FIFO的结构,有效地保证了接口的传输速度.最后给出了电路的ASIC的实现结果.     

新型高可靠性低功耗6管SRAM单元设计

提出一种新型的6管SRAM单元结构,该结构采用读/写分开技术,从而很大程度上解决了噪声容限的问题,并且该结构在数据保持状态下,采用漏电流以及正反馈保持数据,从而不需要数据的刷新来维持数据。仿真显示了正确的读/写功能,并且读/写速度和普通6管基本相同,但是比普通6管SRAM单元的读/写功耗下降了39%。     

An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

A large portion of silicon area and the energy consumed by the Viterbi decoder (VD) is dedicated to the survivor memory and the access operations associated with it. In this work, an efficient pre-traceback architecture for the survivor-path memory unit (SMU) of high constraint length VD targeting wireless communication applications is proposed. Compared to the conventional traceback approach which is based on three kinds of memory access operations: decision bits write, traceback read, and decode read, the proposed architecture exploits the inherent parallelism between the decision bit write and decode traceback operation by introducing pre-traceback operation. Consequently, the proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, compared to the conventional 2-pointer traceback algorithm, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback architecture achieves up to 11.9% energy efficiency and 21.3% area saving compared to the conventional traceback architecture for typical wireless applications.     

A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains

A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18- mum CMOS full-custom design and a 0.18-mum CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580-MHz operation and 10.3-mW power dissipation while performing simultaneous FIFO read and write operations at 1.8 V.     

A VLSI priority packet queue with inheritance and overwrite

Reliable priority-based flow-control is essential for real-time applications involving hard-deadlines. However, the use of first-in-first-out (FIFO) queues in such systems introduces priority inversion resulting in unbounded transmission delays. For this reason, a priority transmission queue is critical for multimedia and mission-critical systems. Yet very few priority queue implementations exist. This paper presents the design of a novel VLSI priority packet queue (PPQ), implemented in 1.2 μm CMOS technology. It achieves fast operation by manipulating its contents in terms of packet segments, rather than individual words. Similar to paged memory, this new segmented architecture greatly reduces implementation cost by reusing segments and avoiding storage area fragmentation. By distributing the computationally intensive priority comparison operation over the access time for an entire segment, the PPQ achieves 96% of the speed of a high-speed packet FIFO. The PPQ can either perform priority inheritance or overwrite lower priority packets to minimize the impact of queue overflow. In addition, it is suitable as a general computer network interface buffer, since it robustly handles asynchronous read and write clocks of greatly disparate frequencies. Our initial implementation achieves well over twice the speed of a nonpipelined approach with minimal additional overhead. Furthermore, scaling this design to larger capacities and more priority levels results in an even greater improvement in speed over conventional approaches     

A new low-power 10T SRAM cell with improved read SNM

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

EPP高速数据采集与LabVIEW接口实现

介绍了EPP高速数据采集的方法及其在LabVIEw下的接口实现。通过直接对端口的操作，可以用LabVIEw直接产生EPP读写时序，配合外部FIFO和握手电路，完成地址的写出与数据的读入。再利用LabVIEW本身的图形工具，可以方便地构成数据的波形显示及对数据的各种处理。     

Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture

In order to reduce static energy consumption, emerging Non-Volatile Memory (NVM) technologies such as Spin Transfer Torque Magnetic RAM (STT-MRAM), Spin-Hall Effect Magnetic RAM (SHE-MRAM), Phase Change Memory (PCM), and Resistive RAM (RRAM) are under intense research. Additionally, there is a demand for more reliable circuits as the technology scales due to increased error rates caused by the increased impact of Process Variation (PV). In order to combat PV-induced reliability problems, a novel approach is proposed herein that improves the reliability of read and write operations in emerging NVMs. In the proposed design, which is called the Self-Organized Sub-bank (SOS) approach, two Sense Amplifiers (SAs) have been adopted, one with improved reliability and one with improved energy efficiency profiles, in order to increase the performance of the read operation. In particular, based on the result of a Power-On Self-Test (POST), which detects PV-impact on sub-banks, SOS chooses between a reliable and an energy-efficient SA and assigns a preferred SA to each sub-bank. Furthermore, in order to increase the performance of the write operation, SHE-MRAM is replaced with STT-MRAM to provide better write energy profile. Additionally, SOS design is once implemented with a reliable write scheme and once with an energy-efficient write scheme and results are compared and analyzed. Based on the preliminary observation in our case study, 21.5% of read operations are extremely vulnerable to PV impacts. Our results indicate that the proposed SOS approach reduces the vulnerability of the read operation by 40% on average, hence reducing the fault propagation. In particular, the SOS alleviates Vulnerable False Data Sensing (VFDS) by 82% on average, while enhancing True Data Sensing (TDS) from 72.5% to 95% across all workloads studied herein compared to LLC with conventional STT-MRAM. Additionally, SOS using the reliable write circuit provides 161% improved Energy Delay Product (EDP) on average compared to SOS with conventional STT-MRAM, while providing less than 8% write current variation. On the other hand, SOS using energy-efficient write circuit offers 39% improved EDP on average compared to the SOS using reliable write circuit and 62% EDP improvement over conventional STT-MRAM.     

A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective cell size including the select transistors is 0.077 /spl mu/m/sup 2/. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm/sup 2/ and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.     

A 20-ns 256 K×4 FIFO memory

A 256 K×4 FIFO (first-in-first-out) CMOS memory with 20-ns access time and 30-ns cycle time is described. To accomplish full static and asynchronous operation, signal synchronizer and arbiter circuits have been developed and implemented into the device. A pair of 120-word×4-bit static memories are furnished to provide 20-ns data access from the very first read cycle. The average current measured at 30-ns read/write operation and the standby current are typically 23 and 1.2 mA, respectively