FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

基于神经元MOS器件的施密特触发器设计

为实现施密特触发器低功耗、回差可控,将神经元MOS器件的控阈技术用于施密特触发器的设计中,设计出基于神经元MOS器件的施密特触发器,并且进一步提出了外部可控回差的施密特触发器的设计.通过HSPICE对电路进行模拟,实验表明此设计仅需2个MOS管,功耗降低30%.并且这种通过改变外部电压值调整回差电压大小的方法比以往的方法更为方便实用.     

基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一.随着电源电压降低,晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响,已经成为制约亚阈值芯片的瓶颈.该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案.该方案首先利用ST的迟滞效应与反馈机制,在电路堆叠结点处添加施密特反馈管以优化逻辑门、减...     

A static power saving TTL-to-CMOS input buffer

This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 μm CMOS process, and the through current is measured to be only 8.9 μA and 11.7 μA for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output upto 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation     

Estimation of high performance in Schmitt triggers with stacking power‐gating techniques in 45 nm CMOS technology

In the complementary metal oxide semiconductor (CMOS) nanoscale technology ground bounce noise and power consumption are becoming important metric. In presented paper, low leakage Schmitt trigger circuits are proposed for wave shaping or cleaning process with low ground bounce noise. Schmitt trigger play important role in communication electronics. Power‐gating and stacking power‐gating techniques have provided for maintaining the parameter of Schmitt trigger. An ideal approach has been investigated with stacking power‐gating technique. For further reduction in peak of ground bounce noise during sleep to active (power) mode transition, we have performed simulations using cadence specter 45 nm standard CMOS technology at nominal temperature (27°C) with supply voltage V_dd = 0.7 V and input voltage vary from 0.7 V to 1.5 V. The simulation results show that a proposed design provide efficient 6 T and 4 T Schmitt triggers in term of minimum leakage power (8.18 fW), active power (17.80 pW), ground bounce noise (1.65 μV) and propagation delay (1.98 ns), transconductance (4.51 × 10^?14 S), voltage gain (29.44 dB), hysteresis width (11.07 V) and efficiency (64.68%). Reported devices use for low‐power communication systems. Copyright © 2013 John Wiley & Sons, Ltd.     

Wide Voltage Input Receiver with Hysteresis Characteristic to Reduce Input Signal Noise Effect

In this paper, an input receiver with a hysteresis characteristic that can work at voltage levels between 0.9 V and 5 V is proposed. The input receiver can be used as a wide voltage range Schmitt trigger also. At the same time, reliable circuit operation is ensured. According to the research findings, this is the first time a wide voltage range Schmitt trigger is being reported. The proposed circuit is compared with previously reported input receivers, and it is shown that the circuit has better noise immunity. The proposed input receiver ends the need for a separate Schmitt trigger and input buffer. The frequency of operation is also higher than that of the previously reported receiver. The circuit is simulated using HSPICE at 0.35‐μm standard thin oxide technology. Monte Carlo analysis is conducted at different process conditions, showing that the proposed circuit works well for different process conditions at different voltage levels of operation. A noise impulse of (V_CC/2) magnitude is added to the input voltage to show that the receiver receives the correct logic level even in the presence of noise. Here, V_CC is the fixed voltage supply of 3.3 V.     

Subthreshold Schmitt trigger using body-bias technique for ultra low power and high performance applications

Digital subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of MOS transistors to operate. In this paper, a body-bias technique to match the subthreshold currents of both the NMOS and PMOS transistors is explored and a Schmitt trigger circuit employing this bias technique is proposed. Extensive circuit simulations were conducted and the results were compared with standard body bias technique in terms of performance parameters. The simulation results were obtained with 0.18 μm technology parameters. The conclusion is that Schmitt trigger with this body biasing is suitable for high performance and ultra low power applications.     

基于开关信号理论的电流型CMOS多值施密特电路设计

以开关信号理论为指导,建立了描述电流型CMOS多值施密特电路中阈值控制电路的电流传输开关运算.在此基础上,提出了新的电流型CMOS三值和四值施密特触发器设计.所设计的电路可提供多值电流和电压输出信号,回差电流的大小只需通过改变MOS管的尺寸比来调节.所提出的电路较之以往设计具有结构简单,回差值调整容易以及可在较低电压下工作等特点.采用TSMC 0.25 μ m CMOS工艺参数和1.5V电压的HSPICE模拟结果验证了所提出设计方案的有效性和电路所具有的理想回差特性.     

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits

This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt trigger circuits in a partially depleted silicon-on-insulator technology. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme, resulting in improved noise immunity and well-defined hysteresis behavior for the Schmitt trigger circuit that is suitable for use as a low-noise receiver, level shifter, waveform-reshaping circuit, and delay element in very large-scale integrated applications.     

Low power Schmitt trigger circuit

Three new Schmitt trigger circuits are described. The first circuit is a truly low power, while the second and third circuits are derived from the first circuit and provide smaller hysteresis width. Measurement results for the new Schmitt trigger circuits are presented. All the designed circuits are simulated using HSPICE with level 28 model parameters for a 1.2 μm standard CMOS technology. An application to the design of low power, very low frequency integrator oscillators is described     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

RS trigger based relaxation oscillator for temperature measurement circuit

Resistance-to-time converter is always used for digital temperature measurement. An reset-set （RS） trigger based, relaxation oscillator based temperature measurement circuit, which is used to convert the change of thermistor sensor into a frequency signal for later processing, has been presented in this article. The RS trigger, which is composed of two inverters designed with distinct logical transition threshold voltages by changing the metal-oxide-semiconductor （MOS） transistor gains, has the same function as the Schmitt trigger in the relaxation oscillator. The advantage of the RS trigger based Schmitt trigger is that it reduces the dependence to supply voltage, chip temperature, and process variation. This temperature measurement circuit has been applied in a clinical thermometer chip that can measure temperature to an accuracy of better than 0.05 ℃ down to 1.1 V battery voltage. It is fabricated in 0.5 μm double metal single poly complementary MOS （CMOS） process.     

Schmitt trigger circuit with picosecond risetimes

A Schmitt trigger circuit is described which overcomes some of the stability problems associated with the wide hysteresis loop of more conventional arrangements. A low level of hysteresis is achieved, thereby reducing the threshold voltage while also affording increased stability during switching. Operational risetimes of 200 ps are demonstrated.     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

CMOS current Schmitt trigger with fully adjustable hysteresis

A CMOS current Schmitt trigger whose hysteresis is independent of process parameters, transistor dimensions and power supplies is described. The hysteresis is determined by two currents and is adjustable over the range of the input current. The circuit function can be extended to a two-input current comparator with adjustable hysteresis.<>     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger circuit has been realised, using only five MOS transistors. The circuit always guarantees hysteresis, even with very large process variations. The switching speed of the new Schmitt trigger is higher, compared to previously reported CMOS Schmitt triggers.     

一种单片低功耗电荷泵电源管理电路的设计

基于0.6 μm BiCMOS工艺,设计了一款高精度电荷泵电源管理芯片.该芯片利用2倍压电荷泵电源转换原理,芯片内部集成了具有优异频率响应的振荡器电容,施密特触发器提供内部精准频率,PFM调制提供稳定的输出电压.测试结果表明,芯片输入电压范围为2.7～5.5V,输出电压为5V,电压纹波小于20 mV,内部振荡频率为700 kHz,低功耗模式时电流仅为6.73 μA.     

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

As the size of CMOS devices is scaled down to lower the power consumption and space occupied on the chip to the nano-scale, unfortunately, noise is not reduced accordingly. As a result, interference due to noise can significantly affect circuit performance and operation. Since noises are random and dynamic in nature, probabilistic noise-tolerant approaches are more desirable to handle this problem. However, trade-offs between hardware complexity and noise-tolerance are severe design challenges in the probabilistic-based noise-tolerant approaches. In this paper, we proposed a cost-effective common-feedback probabilistic-based noise-tolerant VLSI circuit based on Markov random field (MRF) theory. We proposed a common latch feedback method to lower the hardware complexity. To further enhance the noise-tolerant ability, the common latch feedback technique is combined with Schmitt trigger. To demonstrate the proof-of-concept design, a 16-bit carry-lookahead adder was implemented in the TSMC 90 nm CMOS process technology. As compared with the state-of-art master-and-slave MRF design, the experimental results show that not only the transistor count can be saved by 20%, the noise-tolerant performance can also be enhanced from 18.1 dB to 24.2 dB in the proposed common feedback MRF design.     

Differential CMOS Schmitt trigger with tunable hysteresis

This letter presents a new differential Schmitt trigger with tunable hysteresis. The hysteresis is generated using a cross-coupled inverter pair. The amount of hysteresis can be adjusted by varying the current of the symmetrical load. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the triggering voltage of the Schmitt trigger can be adjusted from 0.95 to 1.35 V approximately.     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.