浅沟槽隔离对MOSFET电学特性的影响

随着工艺制程的不断进展,浅沟槽隔离技术(STI)成为深亚微米后的主流隔离技术。文章通过测试分析不同栅到有源区距离(SA)晶体管(MOSFET)器件的栅和衬底电流,分析了180 nm N沟道晶体管中STI对于栅和衬底电流的影响。结果表明栅电流随着SA的缩小呈现先缩小后增大的趋势,衬底电流在常温以及高温下都随着SA的减小而减小。文章用应力机制导致的迁移率以及载流子浓度的变化对栅和衬底电流的变化趋势进行了分析,通过改进伯克利短沟道绝缘栅场效应晶体管模型(BSIM)模拟了STI对衬底电流的影响,为设计人员进行低功耗设计提供了衬底电流模型。     

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

In the present work, a high aspect ratio process (HARP) using a new O₃/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed     

利用显微喇曼光谱进行SiC单晶片应力分析

为了对4H-SiC单晶片进行无损应力表征,采用显微喇曼光谱仪测量了3英寸(1英寸=2.54 cm)和4英寸4H-SiC单晶片的显微喇曼光谱,并依据喇曼频移峰的移动及喇曼频移峰的半高宽(FWHM)分析SiC单晶片中呈现的应力类型和应力大小.在显微喇曼光谱中,4H-SiC单晶片的横向折叠光学(TO)模为表征单晶片应力的特征峰,其无应力状态的标准峰位值为777 cm-1.对4H-SiC单晶片进行应力分析,发现3英寸和4英寸SiC单晶片内喇曼频移峰均发生蓝移和红移,表明单晶片内同时存在张应力和压应力.相比生长初期的样品,晶体生长末期的应力值有不同程度的升高,同时单晶片的喇曼频移峰的FWHM变窄,表明生长末期的单晶片结晶质量高于生长初期.     

Ar Annealing for Suppression of Gate Oxide Thinning at Shallow Trench Isolation Edge

We investigated the effects of high-temperature N₂ and Ar annealing after sacrificial oxidation on the rounding of the top corners in shallow trench isolation (STI). With the N₂ and Ar annealing, the corners were rounded, and the gate oxide thinning was suppressed, indicating that high-temperature annealing in an inert gas ambient is effective for rounding the corners and increasing the gate oxide thickness. With the N₂ annealing, however, the hump in the I_d-V_g curve increased, and the time-dependent dielectric breakdown (TDDB) characteristics were degraded. The possible reason is that the suppression of gate oxidation and/or the oxide quality change occurs at the local spots at the top corners due to the introduction of nitrogen. With the Ar annealing, there was no hump, and the TDDB characteristics improved. It is presumed that the Ar did not accumulate at the sacrificial oxide/substrate interface. Therefore, Ar annealing after gap filling is promising in improving the performance and reliability of transistors with STI.     

Charge Collection by CMOS Transistors from Tracks of Single Particles Passing through Layer of Shallow Trench Isolation

Russian Microelectronics - The features of collecting minority charge carriers formed on the tracks of single particles in a layer of silicon at a depth of 200 to 250 nm under shallow trench...     

阶梯浅沟槽隔离结构LDMOS耐压机理的研究

提出了一种具有阶梯浅沟槽隔离结构的LDMOS.阶梯浅沟槽结构增加了漂移区的有效长度,改善了表面电场及电流的分布,从而提高了器件的击穿电压.借助器件模拟软件Silvaco对沟槽深度、栅长及掺杂浓度等工艺参数进行了优化设计.结果表明,在保证器件面积不变的条件下,新结构较单层浅沟槽隔离结构LDMOS击穿电压提升36%以上,而导通电阻降低14%.     

带浅沟槽隔离的双光电二极管电路模型研究

通过器件模拟并结合实验结果,在已有PIN(Positive intrinsic negative)和DPD(Double photo-diodes)探测器电路模型基础之上,对带浅沟槽隔离(STI)准PIN结构的DPD探测器电路模型进行了探讨。模拟了由深N阱和浅沟槽给DPD带来的性能上的改变,同时结合实验结果,从响应电流和探测器的等效串联电阻两方面对电路模型进行了修正,得到了符合该器件的较准确电路模型。     

Electrical Performance Evaluation of FIB Edited Circuits through Chip Backside Exposing Shallow Trench Isolations

Circuit edit, critical to design validation, is challenged by shrinking dimensions for which an accurate alignment is mandatory. Possible alignment features are in lower metal levels, Poly-silicon and STI structures. STI structures are the first encountered in case of editing through the chip backside and accurate CAD alignment requires trenching until the lower STI edge becomes visible. The impact to device performance in exposing these is examined. Only minor performance changes occur.     

Ge/Si(100)界面互扩散的喇曼光谱

利用喇曼光谱研究了不同温度下在Si(100)衬底上异质外延Ge层由于扩散引起的Ge/Si异质结界面互混以及表面活化剂Sb对其的影响.结果表明表面活化剂Sb的存在大大抑制了界面的互扩散,在650℃下也没有观察到明显的界面互混.没有Sb时,在500℃下已存在一定程度的界面互混,界面互混程度随外延层生长温度的增高而增强.这种互扩散的差别与成岛生长时应变释放有关     

Ge/Si(100)界面互扩散的喇曼光谱

利用喇曼光谱研究了不同温度下在Si(100)衬底上异质外延Ge层由于扩散引起的Ge/Si异质结界面互混以及表面活化剂Sb对其的影响.结果表明表面活化剂Sb的存在大大抑制了界面的互扩散,在650℃下也没有观察到明显的界面互混.没有Sb时,在500℃下已存在一定程度的界面互混,界面互混程度随外延层生长温度的增高而增强.这种互扩散的差别与成岛生长时应变释放有关.     

用高分辨X射线衍射面扫描评估4H-SiC晶片结晶质量

介绍了高分辨X射线衍射(HRXRD)面扫描技术在评估4H-SiC抛光片整体结晶质量方面的应用。对4H-SiC抛光片整片及局部特定位置进行HRXRD摇摆曲线面扫描,并拟合摇摆曲线半高宽(FWHM)峰值得到的极图,观察4H-SiC抛光片表面的FWHM分布范围、分布特点和多峰聚集区。结合表面缺陷测试仪和偏振光显微镜测试方法,对因螺旋生长产生的晶界分布聚集区以及边缘高应力晶界聚集区进行了表征。二者测试结果与HRXRD摇摆曲线面扫描的结果一致。对多片样品在不同区域使用不同测试方法得到的结果均验证了HRXRD摇摆曲线面扫描可以宏观识别晶畴界面聚集区,清楚辨别出位于晶片中心附近由于螺旋生长面交界形成的晶畴界面,以及位于晶片边缘、受生长热场影响晶粒畸变产生的高应力晶畴界面。     

氧含量对RF磁控溅射ZnO薄膜结构特性的影响

采用射频(RF)磁控溅射的方法,通过改变工作气氛中氩气和氧气的比例,在Si(100)衬底上沉积出具有高度C轴择优取向的ZnO薄膜.实验发现随着O2/(Ar+O2)比的增加,薄膜的沉积速率下降.O2/(Ar+O2)比对薄膜结晶状态有明显影响,O2/(Ar+O2)比约为0.45,薄膜结晶质量较好.     

氧含量对RF磁控溅射ZnO薄膜结构特性的影响

采用射频(RF)磁控溅射的方法,通过改变工作气氛中氩气和氧气的比例,在Si(100)衬底上沉积出具有高度C轴择优取向的ZnO薄膜.实验发现随着O2/(Ar O2)比的增加,薄膜的沉积速率下降.O2/(Ar O2)比对薄膜结晶状态有明显影响,O2/(Ar O2)比约为0.45,薄膜结晶质量较好.     

GaAs高温退火过程中热应力对晶体缺陷的影响

用X射线衍射技术分析在高温退火过程中GaAs晶片和石墨接触区域的热应力对晶体缺陷的影响.结果表明:在高温退火条件下,GaAs晶体与石墨接触区域散热不均匀造成的热应力,致使该区域范性形变,从而产生高密度的位错.GaAs晶体中的刃型位错受热应力作用向垂直滑移面的平面移动,聚集后可形成小角晶界,从而导致GaAs晶体的晶格参数和取向均发生变化     

GaAs高温退火过程中热应力对晶体缺陷的影响

用X射线衍射技术分析在高温退火过程中GaAs晶片和石墨接触区域的热应力对晶体缺陷的影响.结果表明:在高温退火条件下,GaAs晶体与石墨接触区域散热不均匀造成的热应力,致使该区域范性形变,从而产生高密度的位错.GaAs晶体中的刃型位错受热应力作用向垂直滑移面的平面移动,聚集后可形成小角晶界,从而导致GaAs晶体的晶格参数和取向均发生变化.     

沟槽栅IGBT非晶Si填槽工艺研究与优化

采用低压化学气相淀积(LPCVD)非晶Si填槽工艺代替LPCVD多晶Si填槽工艺,对沟槽绝缘栅双极型晶体管(IGBT)器件的沟槽进行非晶Si回填,研究并优化了高深宽比非晶Si填槽工艺.分析了LPCVD非晶Si工艺参数如PH3体积流量和沉积时间等对LPCVD非晶Si填槽能力的影响,通过调制P掺杂浓度和优化非晶Si淀积时间,得到槽底侧壁与槽口侧壁非晶Si厚度差值为0.022 μm的基准非晶Si填槽工艺,优化了LPCVD非晶Si反复多次填槽工艺条件.结果表明,采用优化后的工艺可实现沟槽栅IGBT器件沟槽非晶Si无缝回填,器件的栅极电阻降低了0.150 Ω,漏电流降低了1.408 nA,成品率提升了0.4％.     

FEC法生长Si和In双掺GaAs单晶生长技术

研究了几种消除LEC GaAs材料的位错措施以降低温度梯度从而尽可能降低晶体的热应力。掺入等电子In或Si使杂质硬化,为了抑制晶体表面产生位错,开发了全液封切克劳斯基(FEC)晶体生长技术。结合以上三种技术开发出了Si和In双掺FEC GaAs单晶生长技术以消除位错。采用此技术已生长出半导体低位错密度的GaAs晶体,经证实这种掺Si和In低位错GaAs衬底可以满足GaAs LED制作。     

卤素灯快速退火在硅浅结器件中的应用

用卤素灯快速退火工艺代替原始的炉退火工艺,使全离子注入的硅双极浅结器件的杂质浓度更高、结深更浅,从而有效地改善了器件的电参数性能。用这种新工艺制做的分频器,工作频率由原来的1300MHz提高到了1600MHz。该工艺操作方便,节省能源,均匀性、重复性、可控性都大大地优于原始炉退火工艺。     

VB-GaAs单晶中掺Si浓度的控制

低阻GaAs单晶的获得,一般是通过掺入掺杂剂Si来实现的。本文分析了VB-GaAs单晶的掺Si机理及作用,并在理论掺杂公式的基础上,通过实验和理论分析,确定了掺杂剂量的经验关系式。按此公式,在VB-GaAs单晶中得到了理想的掺Si浓度。     

Lifetime Measurement of Excitons in Si by Terahertz Time-domain Spectroscopy with High Spectral Resolution

We have developed an optical pump and terahertz (THz) probe spectroscopy scheme to study the photoexcited dynamics in solids ranging from sub-microsecond to a millisecond regime. We applied the developed scheme to measure the lifetime of long-lived indirect excitons in Si through the observation of intra-exciton transitions, resolving the fine structure of excitons with high spectral resolution in a spectral range from 0.5 to 7 THz (2 to 29 meV). We also performed the lifetime measurement of the lowest energy spin-forbidden dark excitons under the magnetic field. Through the observation of intra-exciton transitions, otherwise inaccessible spin-forbidden dark excitons were directly probed by the THz time-domain spectroscopy. By comparing with the photoluminescence spectroscopy, we revealed that the lowest energy dark excitons are accumulated in the crystal, whereas the recombination dynamics is governed by the nonradiative decay process.