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1.
Evans  I. York  T. 《IEEE sensors journal》2004,4(3):364-372
This paper describes the CMOS circuit design of a sensor for detecting changes of capacitance due, for instance, to the incidence of particles or bubbles on the electrodes. The circuit is based on a simple design originating at the University of California, Berkeley, for measuring crosstalk on integrated circuits. The basic front-end sensor circuit comprises eight MOSFETs and has a sensitivity of 40 mV/fF. A differential amplifier receives the outputs from two sensor circuits each having 20-/spl mu/m square inter-digitated electrodes. The resulting sensitivity of the fabricated sensor is 1 V/fF with a noise level equivalent to 10 aF. Monte Carlo circuit simulations have been used to identify transistor dimensions to yield acceptable yield, and prototype custom silicon chips have been fabricated using a 0.8-/spl mu/m CMOS process. Static and dynamic tests, using polyamide particles as small as 10-/spl mu/m diameter, verify correct operation of the sensors. The sensor is now being developed for application in miniature electrical tomography systems.  相似文献   

2.
A switched-capacitor (SC) interface for capacitive sensors based on a modified Martin's relaxation oscillator is proposed. The output signal is the duty-cycle of a pulse-width modulated square-wave voltage or a binary-coded digital signal which is directly related to the capacitance ratio of an unknown capacitance and reference capacitance. The circuit can be implemented in a monolithic IC form using CMOS technology. It requires a relatively small device count integrable onto a small chip area and its suited particularly for the on-chip interface circuitry for microprocessors  相似文献   

3.
为实现体内压力(如:血压、颅内压等)的实时监测,采用微机电系统(MEMS)技术制造出植入式微压力传感器.由于它是电容式传感器,在信号读取系统中,首先通过集成电路CAV414将电容信号转换为电压信号.通过理论计算和实际试验测试,微压力传感器初始电容值为15 pF.CAV414检测范围是10 pF~2 nF,检测精度为电容初始值的5%,因此在该系统中可检测到的电容最小变化量为0.75 pF,其输出电压范围为0~5 V,该电压信号可以直接作为模拟/数字转换器(ADC)的输入信号.选用ADC0809实现模拟信号向数字信号的转换.ADC0809为一款8通道8位模数转换器,通过FPGA实现对ADC0809的驱动控制.ADC0809的8位输出信号直接作为数字信号的输入,在本文试验中数字信号处理通过FPGA编程实现.  相似文献   

4.
5.
Joseph  D. Collins  S. 《IEEE sensors journal》2007,7(8):1191-1199
Logarithmic CMOS image sensors are appealing for their high-contrast and high-speed response but they require postprocessing to achieve high-quality images. Previously published work has explained the fixed pattern noise (FPN) in these image sensors using a steady-state analysis. This paper explains how the transient response of the readout circuit may also contribute to FPN. Thus, the performance of these CMOS cameras may be optimized with a proper understanding of the transient response, which is explained here through modeling and simulation with some experimental validation. In particular, the gain variation of a logarithmic camera is shown to be caused primarily by premature digitization. As logarithmic and linear active pixel sensors use similar circuits, some results in this paper, e.g., an analysis of readout capacitance, apply equally to the latter.  相似文献   

6.
Resonant tunneling devices are promising candidates for comingling with traditional CMOS circuits, yielding better performance in terms of reduced silicon area, faster circuit speeds, lower power consumption, and improved circuit noise margin. These resonant tunneling devices have several intrinsic merits that include: high current density, low intrinsic capacitance, the negative differential resistance effect, and relative ease of fabrication. In this paper, we briefly describe some circuit configurations of Silicon quantum MOS logic family, with a special emphasis on noise-tolerant design that is now becoming an important constraint for robust and reliable operation of very deep submicron VLSI chips. More specifically, we discuss a novel strategy to incorporate quantum-tunneling devices into mainstream dynamic CMOS circuits with a view to improving the noise immunity of the latter. Dynamic CMOS circuits are rampantly used in modern high-performance VLSI chips achieving the best tradeoff between circuit speed, silicon area, and power consumption. However, they are inherently less noise-tolerant than their static CMOS counterparts. With the continuously deteriorating noise margins due to aggressive down scaling of the CMOS fabrication technologies, the performance overhead due to existing remedial noise-tolerant circuit techniques becomes prohibitively high. In this paper, we propose a novel method that utilizes the negative differential resistance property of quantum tunneling devices. The performance and noise immunity of the proposed circuits are evaluated through both analytical studies and SPICE simulations. We demonstrate that the noise tolerance of dynamic CMOS circuits can be greatly improved with very little degradation in circuit speed. The benefit of the proposed technique is evident even for currently available Silicon-based resonant tunneling devices with a relatively small peak-to-valley current ratio.  相似文献   

7.
The authors have designed, fabricated and successfully tested a Josephson integrated circuit that is used to limit the range of an analog input signal. The circuit consists of a single Josephson junction with a suppressed critical current. The impedance of this suppressed junction consists of the nonlinear quasiparticle resistance in parallel with the capacitance of the junction. The junction capacitance is used to advantage as one pole of a second-order low-pass filter, the other element of which is a thin-film inductor. This filter can perform the function of a slew-rate-limiting filter, at the input to a high-speed comparator. The authors fabricated individual junctions and measured their suppression characteristics and have found that a 2-μm×4.5 μm junction with a nominal critical current of 170 μA can be suppressed to less than 4 μA of critical current with a 14-mA control current. Complete limiter circuits have been fabricated and tested for both their DC and transient characteristics. Measured DC response is in good agreement with simulation, but parasitic capacitance present in the fabricated devices limited the -3 dB bandwidth to about 3.6 GHz  相似文献   

8.
This paper describes the development of micro-capacitors with electrodes based on electrochemically grown vertical gold nanowire arrays. A high aspect-ratio anodized aluminum oxide template integrated on silicon dioxide/silicon substrates was exploited for fabricating a vertical array of nanowires with a high surface to volume ratio. Bismuth ferric oxide thin films were deposited to create high dielectric material between the electrodes using room temperature electrodeposition. This nanofabrication process may be compatible with a complementary metal-oxide-semiconductor (CMOS) process, therefore, this capacitor can be used for protecting and regulating the surge voltage biased to the CMOS circuits. This capacitor achieved a high density capacitance of 3.1 μF/m2 at 1 MHz, which was measured using a parallel plate set-up.  相似文献   

9.
A new technology for remote measuring of vibration sources was recently developed for industrial, medical, and security-related applications [Int. Appl. Patent No: PCT/IL2008/001008]. It requires relatively expensive equipment, such as high-speed complementary metal oxide semiconductor (CMOS) sensors and customized optics. In this paper, we demonstrate how the usage of a simple personal computer (PC) mouse as an optical system composed of a low-power laser and a CMOS circuitry on the same integrated circuit package, can be used to monitor heartbeat from the wrist. The method is based on modifying the mouse optical system in such a way that it will recognize temporal change in skin's vibration profile, generated due to the heart pulses, as mouse movement. The tests that were carried out show a very good correlation between the heartbeat rate measured from human skin and the reference values taken manually.  相似文献   

10.
In this paper, we present a capacitive sensor array for highly integrated lab-on-chip (LoC) applications using the charge-based capacitance measurement method (CBCM). The core-CBCM sensor chip is designed and implemented in 0.18 micron CMOS process featuring an array of capacitive sensors; an offset cancellation module and a low complexity analog-to-digital converter (ADC). This sensor chip is incorporated with a microfluidic channel using direct-write fabrication process. We demonstrate the testing results using chemical solvents with known dielectric constants in order to show the viability of the proposed sensor chip for LoCs.  相似文献   

11.
Two new circuits for the accurate measurement of specimen capacitance and resistive loss are described. The capacitance measurements are unaffected by the specimen resistance when the parallel resistance is greater than 30 ?. The practicality of the circuit is enhanced by its use of coaxial cable to provide both connection to the sample and the inductance required for circuit operation. An important characteristic of the circuit is its ability to measure capacitance and resistance of very high loss specimens accurately.  相似文献   

12.
The recent development of integrated circuit capacitor arrays and the growth of their applications have resulted in a need to perform precision testing as an aid to future design improvements. For reasons discussed in this paper, laboratory instruments such as capacitance bridges are not well-suited to this need. In order to test capacitor arrays accurately, a novel technique has been developed. It is based on a special algorithm in which the capacitor array is used as a precision voltage divider. A capacitor array tester consisting of both hardware and software has been built which executes this algorithm. This system has been used to perform measurements upon a large number (thousands) of NMOS and CMOS capacitor arrays. The standard deviation of this tester's measurement error is approximately 0.0009 percent of full scale (0.0088 LSB referenced to 10 bits). In contrast with manual testing with a capacitance bridge (requiring 10 min per array), the tester requires less than 5 s to fully test an array, mark the circuit and move to the next die position.  相似文献   

13.
This paper presents an easy-to-design interface circuit to measure very small-percentage capacitance variations in capacitive sensors, especially suitable for industrial measurements. A computer-controlled 24-bit A/D converter is employed to obtain a higher resolution. This interface circuit can be used with various types of capacitive sensors. The most interesting thing is, that the measurement results through this interface circuit are independent of the initial capacitance of the sensor. In addition, the double differential operating principle used here minimizes the error caused by coupling and stray capacitance of sensor probes. The operating principle of the designed interface circuit, the major assumptions made, test data, and possible future developments are discussed  相似文献   

14.
This paper describes a novel digital-to-analog (D/A) conversion technique, which uses the analog quantity polarization as a D/A conversion medium. It can be implemented by CMOS capacitors or by ferroelectric capacitors, which exhibit strong nonlinearity in charge versus voltage behavior. Because a ferroelectric material inherently has spontaneous polarization and generally has a large dielectric constant, the effective capacitance of a ferroelectric capacitor is much larger than that of a CMOS capacitor of the same size. This ensures less influence of bottom-electrode parasitic capacitance on a ferroelectric capacitor. Furthermore, a data converter based on ferroelectric capacitors possesses the potential nonvolatile memory function owing to ferroelectric hysteresis. Along with the architecture proposed for polarization-switching digital-to-analog converter (PDAC), its circuit implementation is introduced. Described is implementation of two 9-bit bipolar PDACs: one is based on CMOS capacitors and the other on off-chip ferroelectric capacitors. Experimental results are presented for the performance of these two prototypes.  相似文献   

15.
The present research was motivated by the growing interest of the scientific community towards the understanding of basic gas-surface interaction mechanisms in 1D nanostructured metal oxide semiconductors, whose significantly enhanced chemical detection sensitivity is known. In this work, impedance spectroscopy (IS) was used to evaluate how a top-down patterning of the sensitive layer can modulate the electrical properties of a gas sensor based on a fully integrated nanometric array of TiO(2) polycrystalline strips. The aim of the study was supported by comparative experimental activity carried out on different thin film gas sensors based on identical TiO(2) polycrystalline sensitive thin films. The impedance responses of the investigated devices under dry air (as the reference environment) and ethanol vapors (as the target gas) were fitted by a complex nonlinear least-squares method using LEVM software, in order to find an appropriate equivalent circuit describing the main conduction processes involved in the gas/semiconductor interactions. Two different equivalent circuit models were identified as completely representative of the TiO(2) thin film and the TiO(2) nanostructure-based gas sensors, respectively. All the circuit parameters were quantified and the related standard deviations were evaluated. The simulated results well approximated the experimental data as indicated by the small mean errors of the fits (in the range of 10(-4)) and the small standard deviations of the circuit parameters. In addition to the substrate capacitance, three different contributions to the overall conduction mechanism were identified for both equivalent circuits: bulk conductivity, intergrain contact and semiconductor-electrode contact, electrically represented by an ideal resistor R(g), a parallel R(gb)C(gb) block and a parallel R(c)-CPE(c) combination, respectively. In terms of equivalent circuit modeling, the sensitive layer patterning introduced an additional parameter in parallel connection with the whole circuit block. Such a circuit element (an ideal inductor, L) has an average value of about 125 μH and exhibits no direct dependence on the analyte gas concentration. Its presence could be due to complex mutual inductance effects occurring both between all the adjacent nanostrips (10 μm spaced) and between the nanostrips and the n-type-doped silicon substrate underneath the thermal oxide (wire/plate effect), where a two order of magnitude higher magnetic permeability of silicon can give L values comparable with those estimated by the fitting procedure. Slightly modified experimental models confirmed that the theoretical background, regulating thin film devices based on metal oxide semiconductors, is also valid for nanopatterned devices.  相似文献   

16.
The first measurement of impedance on free-standing diamond films from 0.1 Hz to 10 MHz up to 300℃ were reported. A wide range of chemical vapour deposition (CVD) materials were investigated, but here we concentrate are well fitted to a RC parallel circuit model and the equivalent resistance and capacitance for the diamond films have been estimated using the Zview curve fitting. The results show only one single semicircle response at each temperature measured. It was found that the resistance decreases from 62 MΩ at room temperature to 4 kΩ at300℃, with an activation energy around 0.51 eV. The equivalent capacitance is maintained at the level of 100 pF up to 300℃ suggesting that the diamond grain boundaries are dominating the conduction. At 400℃, the impedance at low frequencies shows a linear tail, which can be explained that the AC polarization of diamond/Au interface occurs.  相似文献   

17.
A fully integrated nanoelectromechanical system (NEMS) resonator together with a compact built-in complementary metal-oxide-semiconductor (CMOS) interfacing circuitry is presented. The proposed low-power second generation current conveyor circuit allows measuring the mechanical frequency response of the nanocantilever structure in the megahertz range. Detailed experimental results at different DC biasing conditions and pressure levels are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing based on nanostencil lithography. The proposed readout circuit can be adapted to operate the nanocantilever in closed loop as a stand-alone oscillator.  相似文献   

18.
The design of a scalable optical local area network formultiprocessing systems is described. Each workstation has aparallel-fiber-ribbon optical link to a centralized complementarymetal-oxide silicon (CMOS) switch core, implemented on a singlecompact printed circuit board (PCB). When the Motorola Optobusfiber technology is used, each workstation has a data bandwidth of 6.4Gbits/s to the core. A centralized switch core interconnecting 32workstations supports a 204-Gbit/s aggregate data bandwidth. Theswitch core is based on a conventional broadcast-and-selectarchitecture, implemented with parallel CMOS integrated circuits(IC's). The switch core scales well; by incorporation of theCMOS optoelectronic IC's with optical input-output, the electricalcore can be reduced to a single-chip optoelectronic IC with terabitcapacities. A prototype of an optoelectronic switch core has been fabricated and is described. The appeal of the architectureincludes its reliance on commercially available parallel-fibertechnology, its reliance on the well-developed markets of local areanetworks and networks of workstations, and its smooth scalability from the electrical to optical domains as technology matures.  相似文献   

19.
This paper presents a circuit system functioning as a capacitance meter suitable for very-high-loss material with a wide range of application in various fields of scientific research and industrial operation. The minimum equivalent parallel resistance of the specimen to be measured reaches as low as 50 ohms and the measuring range of capacitance is from about 0.1 ~ 1000 pF at 2 MHz. Some experimental data are given for the appreciation of its characteristics.  相似文献   

20.
Highly integrated ion-sensitive field-effect transistor (ISFET) microsystems require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip. This paper presents new ISFETs in standard CMOS, fabricated by post-processing of a standard CMOS VLSI chip. Unlike CMOS compatible ISFETs fabricated in a dedicated process, the new sensors are directly combined with state-of-the-art CMOS electronics and are subject to continuous technology upgrading. The ISFETs presented include an intermediate gate formed by one or more conducting layers placed between the gate oxide and the sensing layer. The combination of the highly isolating gate oxide of the MOS with a leaky or conducting sensing layer allows the use of low temperature materials that do not damage the CMOS chip. The operation of ISFETs with an intermediate gate and sensing layers fabricated at low temperature is modeled. ISFETs with a linear pH response and drift as low as 0.3 mV/h are reported.  相似文献   

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