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《固体电子学研究与进展》2013,(5)
借助于SILVACO TCAD仿真工具,研究了高压LDMOS电流准饱和效应(Quasi-saturation effect)的形成原因。通过分析不同栅极电压下漂移区的耗尽情况以及沟道与漂移区电势、电场和载流子漂移速度的分布变化,认为当栅压较低时,LDMOS的本征MOSFET工作在饱和区,栅压对源漏电流的钳制明显,此时沟道载流子速度饱和;而在大栅压下,随着沟道导电能力的增加以及漂移区两端承载的电压的增大,本征MOSFET两端压降迅速降低,器件不能稳定地工作在饱和区而进入线性工作区,此时沟道中的载流子速度不饱和。LDMOS器件的源漏电流的增大主要受漂移区影响,栅压逐渐失去对器件电流的控制,此时增大栅压LDMOS器件的源漏电流变化很少,形成源漏电流的准饱和效应。最后,从器件工作过程对电流与栅压的关系进行了理论分析,并从理论结果对电流准饱和效应进行了深入分析。 相似文献
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GaAs MESFET栅极漏电流退化机理分析 总被引:2,自引:2,他引:0
高温存储试验后某种GaAs MESFET的栅-漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅-漏极低压正向电流随温度的变化,定性估计了试验前后复合-产生中心浓度的变化,确定肖特基势垒接触有源层的复合-产生中心浓度增加是两种漏电流增大的原因,为高温下GaAs MESFET的肖特基势垒接触存在栅金属下沉和扩散提供了证据。 相似文献
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针对GaAsMESFET在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了TiAl栅和TiPtAu栅GaAs MESFET的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的经是导致器件的跨导gm、栅反向漏电流Is、夹断电压Vp等特性退化,甚至导致器件烧毁失效的主要原因。 相似文献
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高温正向大电流下TiAl、TiPtAu栅GaAs MESFET的栅退化机理及其对器件特性的影响 总被引:1,自引:1,他引:0
针对GaAs MESFET在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了Tial栅和TiPtAu栅GaAs MESFET的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的退化是导致器件的跨导gm、栅反向漏电流Is、夹断电压Vp等特性退化,甚至导致器件烧毁失效的主要原因。 相似文献
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高温存储试验后某种GaAs MESFET的栅-漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅-漏极低电压正向电流随温度的变化,定性估计了试验前后复合-产生中心浓度的变化,确定肖待基势垒触有源层的复合-产生中心浓度的增加是两种漏电流增大的原因,为高温下GaAs MESFET的肖特基势垒接触存在栅金属下沉和扩散提供了证据. 相似文献
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双极场引晶体管:Ⅲ.短沟道电化电流理论(双MOS栅纯基) 总被引:1,自引:1,他引:0
本文描述双极场引晶体管(BiFET)短沟道理论.晶体管分成两个区域,源区和漏区.每区在特定外加端电压下既可为电子或空穴发射区又可为电子或空穴收集区.把两维无缺陷Shockley方程分离为两个以表面势为参变量的一维方程,并运用源区和漏区界面处电子电流和空穴电流连续性,得到在源区和漏区内解析方程.典型BiFET包括薄纯基上两个等同金属氧化物硅(MOS)栅.用图形提供实用硅基和氧化层厚度范围内,随直流电压变化,输出和转移电流和电导总量,电子沟道与空穴沟道分量,和两区电学长度.报道前没考虑沟道缩短的偏差. 相似文献
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Hasumi Y. Matsunaga N. Oshima T. Kodera H. 《Electron Devices, IEEE Transactions on》2003,50(10):2032-2038
Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion. 相似文献
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E.F. Stikvoort 《Solid-state electronics》1979,22(6):595-598
A new device for mixing in the VHF range is presented which has very low third-order distortion. The device consists of a DMOST having a polysilicon resistive gate which is biased by a d.c. current that flows at right angles to the source to drain current in the DMOST. As a result of this gate bias current the device has a drain current to input gate voltage characteristic with a large square low region when the drain operates above the “pinch off” voltage. Samples of the device exhibit an extremely quadratic behaviour over several volts of the input gate voltage. 相似文献
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Gate current in OFF-state MOSFET 总被引:1,自引:0,他引:1
The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure 相似文献
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A p-channel poly-Si/Si1-xGex/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si1-xGex/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si1-xGex material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current 相似文献
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《Electron Devices, IEEE Transactions on》1972,19(2):213-219
There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx ) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi , the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Vi and Vtx the surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx . The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed. 相似文献
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Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for VFB < VG < 0 V and the second for VG < VFB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage. 相似文献
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The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET 相似文献
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N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta2O5 gate dielectric were fabricated. An intrinsic Ta2O5/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta 2O5/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage VDS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode 相似文献