高补偿硅的阻-温特性

采用5·cm的p型单晶硅,通过在高温下扩散金属锰的方法,可以得到高补偿硅。笔者选择没有光照下,室温电阻率为5.84×104·cm的样品,进行测量电阻随温度的变化关系(温度从77 K上升到300 K)。测试结果表明:在没有光照条件下测试时,电阻随温度的变化同普通的半导体;但在受到光照时,却出现极不相同的情况,这种不同,可能来自所掺杂的硅是一种光敏材料及掺入的杂质是一种深能级杂质。     

霍尔测试估计含氮直拉硅单晶中的氧施主

本文对含氮ＣＺ硅单晶中的氧施主进行了探讨，测试样品是６５０℃下处理的含氮ＣＺ硅单晶在７００℃的温度下继续热处理。通过变温霍尔测试发现，材料中除了热施主外，还存在一种浅施主能级。这种浅施主在６５０℃下不能完全消除，７００℃下继续处理浓度减少而引起电阻率上升。     

高补偿硅的阻–温特性

采用5Ω·cm的p型单晶硅,通过在高温下扩散金属锰的方法,可以得到高补偿硅.笔者选择没有光照下,室温电阻率为5.84×104Ω·cm的样品,进行测量电阻随温度的变化关系(温度从77 K上升到300 K).测试结果表明:在没有光照条件下测试时,电阻随温度的变化同普通的半导体;但在受到光照时,却出现极不相同的情况,这种不同,可能来自所掺杂的硅是一种光敏材料及掺入的杂质是一种深能级杂质.     

补偿硅的温度敏感特性

采用低电阻车的p型单晶硅,在高温条件下扩散金属锰的方法,可以得到高补偿和过补偿硅。在常温下,测试扩散后电阻率分别为3.2×10~3、4.8×10~4、1.3×10~5、3.2×10~5Ω·cm的几种样品的温度敏感特性,其相应的B值分别为5103,5600,6103,6502 K。这种扩锰硅是一种温度敏感材料,笔者将报道这些实验结果并讨论其热敏特性。     

受主掺杂对TiO2氧敏材料缺陷化学的影响

对受主B2O5掺杂TiO2材料的高温电导进行了详细的测试；XRD分析表明少量受主掺杂并未改变材料的金红石结构；对比施主掺杂研究，出现了很多有趣的现象。施主掺杂样品在较高的测试温度（约950℃）下发生电导类型转变，而受主掺杂样品在较低的测试温度（约750℃）下发生电导类型转变。应用电子补偿及缺位补偿机制对电导特性进行了分析。     

退火对Mn-Co-Ni-O薄膜器件性能的影响

采用磁控溅射法制备了厚度为6.5μm的Mn_(1.95)Co_(0.77)Ni_(0.28)O_4组分的薄膜材料,把材料分别在400℃,500℃,600℃,700℃,800℃下进行后退火处理.结果表明,室温下的负电阻温度系数α295值随退火温度增加先增大后减小,而电阻率ρ_(295)则是随退火温度增加逐渐减小的;在相同频率下,500℃退火样品的归一化噪声谱密度(S_V·V_R/V~2)最小,700℃退火样品的归一化噪声谱密度最大.退火温度越高会造成越多的晶体缺陷,从而降低有效导热系数、增大时间常数τ和器件噪声.     

碲镉汞晶体补偿度的研究

对于8～14微米Hg_(1-x)Cd_xTe晶体材料,已测量了4.2～300 K温度范围内的霍尔系数和电阻率,获得了载流子浓度和迁移率随温度变化的关系。在载流子浓度非完全简并的条件下,根据杂质饱和电离散射所确定的迁移率,计算了三个样品的补偿度。并且通过电中性方程验算了迁移率法计算补偿度的准确性。     

Zn掺杂n型硅材料的补偿研究

为了获得不同补偿度的硅材料,采用高温气相扩散的方法,在n型硅中掺杂深能级杂质Zn,得到各种电阻率(在25℃下)的补偿硅。实验表明,对具有不同初始电阻率的硅材料,扩散后电阻率随扩散温度和杂质投入量的不同都有较大变化,而且随杂质投入量的增加,电阻率都有一个急剧变化的转折点。     

深能级杂质Zn对n型硅半导体的补偿特性

为得到高B值(材料常数)的单晶热敏材料,采用高温气相扩散的方法在n型硅中掺杂深能级杂质Zn,得到高补偿的硅材料,并对该材料特性进行了测试和分析.结果表明:这种补偿硅具有热敏特性,该材料的B值为6300K左右,其阻值对温度的依赖关系与杂质的补偿程度有关.     

自由电子激光对GaAs/AlGaAs异质结构材料电学性质的影响

自由电子激光(FEL)辐照样品前和辐照样品时,使用变温霍尔测量系统测试了这种n型调制掺杂GaAs/AlGaAs异质结构材料中准二维电子气(2DEG)的迁移率、电子浓度和电阻率。对比这两种情况下的结果可以发现:1)迁移率随温度升高而降低,光照使迁移率增大;2)电子浓度随温度变化关系相对较为复杂,但是平均而言,光照会使电子浓度减小;3)电阻率随温度升高而升高,光照使电阻率减小,但这种影响不明显。对这些现象给出了具体的分析。     

20·5% efficient silicon solar cell with a low temperature rear side process using laser‐fired contacts

The paper presents a rear side structure for crystalline silicon solar cells, which is processed at a maximum temperature of 220°C. Using two different material compositions for electrical and optical needs, the layer system has excellent passivation properties, enhances light trapping and allows for a good ohmic contact. With this structure we achieve an independently confirmed conversion efficiency η=20·5% on a 250 μm thick silicon solar cell. Due to the fact that the maximum process temperature is 220°C, this layer system enables new solar cell concepts. Copyright © 2006 John Wiley & Sons, Ltd.     

Characterization of an Oxidized Porous Silicon Layer by Complex Process Using RTO and the Fabrication of CPW‐Type Stubs on an OPSL for RF Application

This paper proposes a 10‐µm thick oxide layer structure that can be used as a substrate for RF circuits. The structure has been fabricated using an anodic reaction and complex oxidation, which is a combined process of low‐temperature thermal oxidation (500 °C, for 1 hr at H₂O/O₂) and a rapid thermal oxidation (RTO) process (1050 °C, for 1 min). The electrical characteristics of the oxidized porous silicon layer (OPSL) were almost the same as those of standard thermal silicon dioxide. The leakage current density through the OPSL of 10 µm was about 10 to 50 nA/cm² in the range of 0 to 50 V. The average value of the breakdown field was about 3.9 MV/cm. From the X‐ray photo‐electron spectroscopy (XPS) analysis, surface and internal oxide films of OPSL prepared by a complex process were confirmed to be completely oxidized. The role of the RTO process was also important for the densification of the porous silicon layer (PSL) oxidized at a lower temperature. The measured working frequency of the coplanar waveguide (CPW) type short stub on an OPSL prepared by the complex oxidation process was 27.5 GHz, and the return loss was 4.2 dB, similar to that of the CPW‐type short stub on an OPSL prepared at a temperature of 1050 °C (1 hr at H2O/O2). Also, the measured working frequency of the CPW‐type open stub on an OPSL prepared by the complex oxidation process was 30.5 GHz, and the return was 15 dB at midband, similar to that of the CPW‐type open stub on an OPSL prepared at a temperature of 1050 °C (1 hr at H₂O/O₂).     

微波退火非晶硅薄膜低温晶化研究

多晶硅薄膜晶体管以及其独特的优点在液晶显示领域中起着重要的作用。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（＜600℃高质量多晶硅薄膜已成为研究热点。文章研究了一种低温制备多晶硅薄膜的新工艺;微波退火非晶硅薄膜固相晶化法,利用X射线衍射、拉曼光谱和扫描电镜分析了微波退火工艺对非晶硅薄膜固相晶化的影响,成功实现了低温制备多晶硅薄膜。     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

Correlation between excess Si atoms near the ultrathin silicon oxide-Si(100) interface and oxidation temperature

The number densities (areal densities) of Si and O atoms for 3.5–8.0-nm-thick silicon oxide films on Si(100) oxidized at 800–950 C were determined by Rutherford backscattering spectrometry. It was confirmed that excess Si atoms relative to the stoichiometric SiO₂ composition exist near the oxide film-Si substrate interface and the oxidation temperature vs. their number density (N_Si(excess)) characteristic exhibits a minimum at 850 C. This oxidation temperature dependence contrasted with that for volumetric density; a maximum at 850 C. Moreover, a slight discrepancy of the oxide thickness (ΔT_ox), which probably corresponds to the slight microscopic structural change due to the N_Si(excess) difference, decreased with decreasing oxidation temperature without showing a minimum at 850 C. Therefore, although most of the fundamental characteristics for the ultrathin oxide faithfully follow the change of N_Si(excess), in the 800 C-oxidation films, it was suggested that N_Si(excess) is possibly increased by additional structural changes without increasing ΔT_ox.     

Residual disorder in low-temperature polycrystalline silicon

Polycrystalline silicon, widely used so far as current line material in microelectronics, has recently become a promising candidate for thin films devices (transistor, solar cell). In all these applications, low-temperature fabrication (< 600°C) will represent a significant progress. This was achieved through two ways : (i) by assisting the thermal decomposition of silane with a diode hf plasma ; the temperature threshold of polycrystalline deposition is decreased down to 350°C; (ii) by purely thermal deposition of an amorphous film at 620°C, then in situ recrystallization at 400°C through exposure to a hydrogen plasma, which on the other hand passivates the grain boundaries. We report the correlative variations of the grain size (x-ray), the residual short range disorder (Raman) and the H content (Elastic Recoil Detection) for these various poly-Si preparations. Posthydrogenation is shown to relax the Si matrix. The Raman line widening previously attributed to crystallite size below a few 10² Å is shown here to originate from residual short range disorder in the material. At this moment, poly-Si films obtained at low temperature exhibit higher residual disorder than those obtained from pure LPCVD at high temperature. Moreover, depending on the preparation, additional disorder is shown to appear at the surface and interface of all polycrystalline films.     

（英）退火温度对电子束蒸发沉积硅薄膜结构和光学性能的影响

系统研究了退火温度对硅薄膜结构和光学性能的影响。通过电子束蒸发工艺制备硅薄膜,然后在氮气保护下对薄膜样品在200~500°C范围内进行退火处理。使用XRD、拉曼光谱、电子自旋共振和透射光谱测量等方法对薄膜样品进行了表征。结果显示,随着退火温度的升高,非晶硅薄膜结构有序度在短程和中程范围内得到改善,同时缺陷密度显著降低-。当样品在400°C退火后,消光系数k由6.14×10^-3下降到最小值1.02×10~3(1000 nm),这是由于此时硅薄膜缺陷密度也降到最低,约为沉积态薄膜的五分之一。试验结果表明,硅薄膜在适当的温度下退火可以有效地降低近红外区膜层的光学吸收,这对硅薄膜在光学薄膜器件研制中具有重要应用。     

Dopant activation and surface morphology of ion implanted 4H- and 6H-silicon carbide

The activation of ion-implanted B into 4H-SiC, and B, and Al into 6H-SiC is investigated. Complete activation of B implants into 4H-SiC is achieved by annealing at 1750°C for 40 min in an Ar environment. Significant activation (>10%) is not achieved unless the annealing temperature is 1600°C or greater. Sheet resistances of Al-implanted 6H-SiC annealed at 1800°C are 32.2 kΩ/□, indicating high activation of Al at this temperature. Annealing conditions which result in good acceptor activation are shown to be damaging to the surface of either 4H- or 6H-SiC. Atomic force microscopy and Nomarski differential interference contrast optical microscopy are applied to characterize the surfaces of these polytypes. Roughening of the surfaces is observed following annealing in Ar, with measured roughnesses as large as 10.1 nm for B-implanted 4H-SiC annealed at 1700°C for 40 min. Based on data obtained from these techniques, a model is proposed to describe the roughening phenomenon. The premise of the model is that SiC sublimation and mobile molecules enable the surface to reconfigure itself into an equilibrium form.     

Porous silicon as an intermediate buffer layer for GaN growth on (100) Si

We report preliminary results on the growth of GaN on (100) Si substrate using porous silicon (PS) as an intermediate buffer layer. The growth was in situ monitored by laser beam reflectivity. Analysis of the evolution of the reflectivity signal indicates a change from relatively flat surface to rough one as the growth temperature (T_g) is increased. At a temperature of about 1050°C, the growth rate is very low and the reflected signal intensity is constant. When the growth temperature is varied, no drastic change of the porosity of the intermediate layer was detected. Scanning electron microscope (SEM) observations of the GaN/SP/Si structure revealed a good surface coverage at 500°C. When T_g increases, the structure morphology changes to columnar like structure at 600°C, and well-developed little crystallites with no preferential orientation appear at 800°C. These observations agree well with the X-ray diffraction (XRD) analysis. A preferential hexagonal growth is obtained at low growth temperature, while cubic phase begin to appear at elevated temperatures.     

Structural and electrical properties of polycrystalline silicon films deposited by low pressure chemical vapor deposition with and without plasma enhancement

Silicon thin films prepared by chemical vapor deposition of silane at very low pressures (4 mTorr) in an experimental reactor that allows deposition with and without plasma enhancement have been characterized. The temperature range of the substrates on which the films were deposited was varied from 500 to 800° C for plasma-enhanced depositions and 600 to 800° C for nonplasma depositions. Conductivity measurements as a function of temperature as well as average grain size and crystallographic texture measurements were performed. The results indicate that the films deposited with the assistance of a plasma were amorphous at deposition temperatures of 650° C and below and polycrystalline at deposition temperatures of 700° C and above. In the temperature regime investigated, this amorphous-to-crystalline transition was not observed in films deposited without the assistance of a plasma. Furthermore, all the films deposited at temperatures of 650° C and below have been found to have significantly different properties from the similarly prepared films deposited at higher temperatures.