A Reduced Delay Method for Improving the Performance of Sigma-Delta Analog-to-Digital Converters (ADC)

Excess loop delay in a continuous-time switched-current modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the predicted next state to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6–10 dB improvement in dynamic range for a second-order modulator.     

Floor acquisition multiple access (FAMA) in single‐channel wireless networks

The FAMANCS protocol is introduced for wireless LANs and adhoc networks that are based on a single channel and asynchronous transmissions (i.e., no time slotting). FAMANCS (for floor acquisition multiple access with nonpersistent carrier sensing) guarantees that a single sender is able to send data packets free of collisions to a given receiver at any given time. FAMANCS is based on a threeway handshake between sender and receiver in which the sender uses nonpersistent carrier sensing to transmit a requesttosend (RTS) and the receiver sends a cleartosend (CTS) that lasts much longer than the RTS to serve as a busy tone that forces all hidden nodes to back off long enough to allow a collisionfree data packet to arrive at the receiver. It is shown that carrier sensing is needed to support collisionfree transmissions in the presence of hidden terminals when nodes transmit RTSs asynchronously. The throughput of FAMANCS is analyzed for singlechannel networks with and without hidden terminals; the analysis shows that FAMANCS performs better than ALOHA, CSMA, and all prior proposals based on collision avoidance dialogues (e.g., MACA, MACAW, and IEEE 802.11 DFWMAC) in the presence of hidden terminals. Simulation experiments are used to confirm the analytical results.     

The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain

This article introduces ATR's CAM-Brain Machine (CBM), an FPGA based piece of hardware which implements a genetic algorithm (GA) to evolve a cellular automata (CA) based neural network circuit module, of approximately 1,000 neurons, in about a second, i.e. a complete run of a GA, with 10,000 s of circuit growths and performance evaluations. Up to 65,000 of these modules, each of which is evolved with a humanly specified function, can be downloaded into a large RAM space, and interconnected according to humanly specified artificial brain architectures. This RAM, containing an artificial brain with up to 75 million neurons, is then updated by the CBM at a rate of 130 billion CA cells per second. Such speeds should enable real time control of robots and hopefully the birth of a new research field that we call brain building. The first such artificial brain, to be built by ATR starting in 2000, will be used to control the behaviors of a life sized robot kitten called Robokoneko.     

Scheduling and bandwidth allocation for the distribution of archived video in VOD systems

Providing costeffective videoondemand (VOD) services necessitates reducing the required bandwidth for transporting video over highspeed networks. In this paper, we investigate efficient schemes for transporting archived MPEGcoded video over a VOD distribution network. A video stream is characterized by a timevarying traffic envelope, which provides an upper bound on the bit rate. Using such envelopes, we show that video streams can be scheduled for transmission over the network such that the perstream allocated bandwidth is significantly less than the source peak rate. In a previous work [13], we investigated stream scheduling and bandwidth allocation using global traffic envelopes and homogeneous streams. In this paper, we generalize the scheduling scheme in [13] to include the heterogeneous case. We then investigate the allocation problem under windowbased traffic envelopes, which provide tight bounds on the bit rate. Using such envelopes, we introduce three streamscheduling schemes for multiplexing video connections at a server. The performance of these schemes is evaluated under static and dynamic scenarios. Our results indicate a significant reduction in the perstream allocated bandwidth when stream scheduling is used. While this reduction is obtained through statistical multiplexing, the transported streams are guaranteed stringent, deterministic quality of service (i.e., zero loss rate and small, bounded delay). In contrast to video smoothing, our approach requires virtually no buffer at the settop box since frames are delivered at their playback rate.     

A Markov modulated fluid queueing system with strict priority

We investigate a Markov modulated fluid queueing system with strict priority. The input process is composed of two fluid flows which are stored in buffer1 and buffer2, respectively. The rates of these fluid flows depend on the current state of a finite state Markov chain. Buffer1 has full assignment of priority (=strict priority) for service and so buffer2 is served at a residual service rate when buffer1 is empty. We explicitly derive the stationary joint distribution of the two buffer contents in the system by a spectral decomposition method. In the case of a twostate Markov chain, the joint distribution is explicitly expressed in terms of the system parameters. Also the joint moments and tail distributions of the two buffer contents are obtained and some numerical examples are presented.     

Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

Predictive Caching Strategy for On-Demand Routing Protocols in Wireless Ad Hoc Networks

Route caching strategy is important in on-demand routing protocols in wireless ad hoc networks. While high routing overhead usually has a significant performance impact in low bandwidth wireless networks, a good route caching strategy can reduce routing overheads by making use of the available route information more efficiently. In this paper, we first study the effects of two cache schemes, link cache and path cache, on the performance of on-demand routing protocols through simulations based on the Dynamic Source Routing (DSR) protocol. Since the path cache DSR has been extensively studied, we focus in this paper on the link cache DSR in combination with timer-based stale link expiry mechanisms. The effects of different link lifetime values on the performance of routing protocol in terms of routing overhead, packet delivery ratio and packet latency are investigated. A caching strategy incorporating adaptive link timeout is then proposed, which aims at tracking the optimal link lifetime under various node mobility levels by adaptively adjusting the link lifetime based on the real link lifetime statistics. The performance of the proposed strategy is then compared with the conventional path cache DSR. The results show that without a timeout mechanism, a link cache scheme may suffer severe performance degradation due to the use of broken routes, while the proposed adaptive link cache strategy achieves significantly improved performance by reducing the routing overhead when the network traffic load is high.     

Personal Imaging and lookpainting as tools for personal documentary and investigative photojournalism

A means and apparatus for covert capture of extremely highresolution photorealistic images is presented. The apparatus embodies a new form of userinterface – instead of the traditional point and click metaphor which was thought to be the simplest photography had to offer, what is proposed is a look metaphor in which images are generated through the natural process of looking around, in a manner that does not require conscious thought or effort. These lookpaintings become photographic/videographic memories that may, at times, exceed the quality attainable with even large and cumbersome professional photographic film cameras, yet they may be captured through a device that resembles ordinary sunglasses. The method is based on longterm psychophysical adaptation using a covert sunglassbased realitymediating apparatus, together with two new results in image processing. The first new result is a means of estimating the true projective coordinate transformation between successive pairs of images, and the second is that of estimating, to within a single unknown scalar constant, the quantity of light arriving at the image plane. Furthermore, what is captured is more than just a picture. The resulting environment map may be explored by one or more remote participants who may also correspond and interact with the wearer during the actual shooting process, giving rise to computer supported collaborative (collective) photography, videography, shared photographic/videographic memory, etc.     

Editorial

Future integrated microsystems will benefit significantlyfrom progress in the VLSI field. Two key elements will boostthe implementation of new micro-integrated architectures: progressin batch-manufactured silicon sensors and the introduction ofnew circuit techniques for designing interface circuits. Thesetwo factors will be essential in favoring the transition fromthe present research driven speculations to customer drivenactivities. This paper discusses the key issues in realizingmicrosensors and the most suitable circuit techniques for interfacingand processing their output signals. A number of examples ofintegrated structures will illustrate present problems and possiblesolutions.     

Economics of “design for test” to remain competitive in the 90s

This article emphasizes the criticality of maximizing value adders and minimizing the costs of design for test (DFT) in order to remain competitive in ASIC manufacturing in the 90s.     

Mobile ATM buffer capacity analysis

This paper extends a stochastic theory for buffer fill distribution for multiple on and off sources to a mobile environment. Queue fill distribution is described by a set of differential equations assuming sources alternate asynchronously between exponentially distributed periods in on and off states. This paper includes the probabilities that mobile sources have links to a given queue. The sources represent mobile user nodes, and the queue represents the capacity of a switch. This paper presents a method of analysis which uses mobile parameters such as speed, call rates per unit area, cell area, and call duration and determines queue fill distribution at the ATM cell level. The analytic results are compared with simulation results.This paper is partially funded by ARPA contract number J-FBI-94-223.The Mathematica code for this paper can be found on http://www.tisl.ukans.edu/sbush.     

Shorts of block operators and infinite networks—A note on the shorted operator: II

Let A_ij i, j=1, 2,..., be operators on a Hilbert spaceX, such that the compound operatorA =A _{ij i, j=1} induces a bounded positive operator onl ₂(X). We show that S(A , theshorted operator (orgeneralized Schur complement), of A can be obtained as the limits of shorts of the operators A_n, where A_n is the truncated version ofA , thenA _n=A _{ij i, j=1} ⁿ . We use these results to study the short-circuit approximations to infinite networks.     

Simulation‐based performance evaluation of routing protocols for mobile ad hoc networks

In this paper we evaluate several routing protocols for mobile, wireless, ad hoc networks via packetlevel simulations. The ad hoc networks are multihop wireless networks with dynamically changing network connectivity owing to mobility. The protocol suite includes several routing protocols specifically designed for ad hoc routing, as well as more traditional protocols, such as link state and distance vector, used for dynamic networks. Performance is evaluated with respect to fraction of packets delivered, endtoend delay, and routing load for a given traffic and mobility model. Both small (30 nodes) and medium sized (60 nodes) networks are used. It is observed that the new generation of ondemand routing protocols use much lower routing load, especially with small number of peertopeer conversations. However, the traditional link state and distance vector protocols provide, in general, better packet delivery and endtoend delay performance.     

On the design of feedback controllers to achieve prescribed initial value constraints

The problem of designing a stabilizing compensator for a control system to achieve prescribed initial value constraints ⁽ⁱ⁾(0⁺)=y_i is considered. Indeed, modulo certain technical conditions, such a compensator exists if and only if y_i=0;i= 0,1,...,rp +rt –2; whererp is the relative degree of the plant andrt is the relative degree of the system input. This theorem is derived and a complete parameterization of the set of compensators that achieve the prescribed design constraints is formulated.This research was supported in part by NSF Grant No. 921106.     

Microsystems Engineering: A Great Stride Forward in Microelectronics Technology

The development of new-generation technological and engineering concepts by the example of microsystems technology and microsystems engineering approaches is considered.     

A scalable wireless virtual LAN

This paper presents a Wireless Virtual Local Area Network (WVLAN) to support mobility in IPoverATM local area networks. Mobility is handled by a joint ATMlayer handoff for connection rerouting and MAClayer handoff for location tracking, such that the effects of mobility are localized and transparent to the higherlayer protocols. Different functions, such as Address Resolution Protocol (ARP), mobile location, and ATM connection admission are combined to reduce protocol overhead and frontend delay for connectionless packet transmission in connectionoriented ATM networks. The proposed WVLAN, through the use of ATM technology, provides a scalable wireless virtual LAN solution for IP mobile hosts.     

The Future Generations of Mobile Communications Based on Broadband Access Methods

The forthcoming mobile communication systems are expected to provide much variety of services from high quality voice to high definition videos through high data rate wireless channels at anywhere in the world. High data rate requires broad frequency bands, and sufficient broadband can be achieved in higher frequency bands such as microwave, Ka-band and millimeter-wave. Broadband wireless channels have to be connected to broadband fixed networks such as the Internet and local area networks. The future generation systems will include not only cellular phones, but also many new types of communication systems such as broadband wireless access systems, millimeter-wave LAN, intelligent transport systems (ITS) and high altitude stratospheric platform station (HAPS) systems. The key words in the future generations of mobile communications are multimedia communications, wireless access to broadband fixed networks and seamless roaming among different systems. This article discusses the future generations mobile communication systems.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.