Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

Use of the polysilicon gate layer for local interconnect in a CMOStechnology incorporating LDD structures

In conventional single-level polysilicon technologies, the polysilicon gate layer can be used as an interconnect layer through buried contacts between polysilicon and one type of junction (usually n ⁺) in the underlying substrate. The formation and characteristics of buried contacts between n⁺ and p⁺ junctions and a single polysilicon gate layer are discussed. In addition, it is shown that the obstacles posed by the inclusion of oxide-sidewall spacers (common in present-day VLSI CMOS technologies) are surmountable with respect to the formation of useful buried contacts and the resultant local interconnect level that they provide     

Study of the extended p+ dual source structure foreliminating bipolar induced breakdown in submicron SOI MOSFET's

Simulation results on a novel extended p⁺ dual source SOI MOSFET are reported. It is shown that the presence of the extended p ⁺ region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p⁺ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's     

A Novel Body-tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current (I_DS-V_DS) curves, substrate resistance effect on the I_DS-V_DS curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET

For the first time, we report the combined application of a SiGe source and a delta-doped p⁺ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

SATPOLY: a self-aligned tungsten on polysilicon process for CMOSVLSI applications

The use of complementarily doped n⁺ and p⁺ polysilicon has been proposed for future generations of CMOS technology. The implementation of this technology requires low-resistance shunts both to reduce the overall resistance of the gate level interconnections and to short out the polysilicon p-n junctions. A process in which tungsten is chosen to provide the low-resistance shunts, with the necessary gate sidewall spacers formed before the selective deposition of tungsten, is described. A nonselective tungsten deposition process, originally developed explicitly for the implementation of direct tungsten gate MOS technology, is a key step in the formation of the spacers in the SATPOLY (self-aligned tungsten on polysilicon) process. The work function stability and the adhesion of the tungsten-polysilicon double-layer structure as a function of the polysilicon glue layer thickness have also been investigated     

Extremely scaled double-gate CMOS performance projections,including GIDL-controlled off-state current

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n⁺ and p⁺ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p⁺ -gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

Strong Efficiency Improvement of SOI-LEDs Through Carrier Confinement

Contemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts. In this letter, we present a new device structure where the carrier injection takes place through silicon slabs of only a few nanometer thick. Its external quantum efficiency of 1.4middot10^-4 at room temperature, with a spectrum peaking at 1130 nm, is almost two orders higher than reported thus far on SOI. The structure diminishes the dominant role of nonradiative recombination at the n⁺ and p⁺ contacts, by confining the injected carriers in an SOI peninsula. With this approach, a compact infrared light source can be fabricated using standard semiconductor processing steps     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n⁺ polysilicon gate, and p⁺ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm²/V-s at 300 K and 980 cm²/V-s at 82 K were achieved in functional submicrometer p-MOSFETs     

LDD MOSFETs using disposable sidewall spacer technology

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n^- and n⁺ or p^- and p⁺ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K×4 SRAM circuit using a conventional 1.5-μ CMOS technology     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Flatband voltage shift in PMOS devices caused by carrier activationin p+-polycrystalline silicon and by boron penetration

After discovering that the annealing-time dependence of the flatband voltage shifts of a p⁺-polysilicon gate MOS diode can be attributed to boron activation in polysilicon instead of boron penetration through gate M₂, we proposed a boron activation model for polysilicon in which the carrier activation is related to the grain size of the polysilicon. Using this model, we analyzed the characteristics of pMOSFETs with polysilicon gates of different grain sizes and found that they depend on the grain size, as expected. Using the model, we quantitatively identified process windows for p⁺-polysilicon gate pMOSFETs, assuming that enough boron is activated in the polysilicon without the boron penetrating through the gate SiO₂     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Ultrafast operation of Vth-adjustedp+-n+ double-gate SOI MOSFET's

To optimize the V_th of double-gate SOI MOSFET's, we fabricated devices with p⁺ poly-Si for the front-gate electrode and n⁺ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V_th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects