On the stability of local scheduling policies in networks of packet switches with input queues

A significant research effort has been devoted to the design of simple and efficient scheduling policies for input queued (IQ) and combined input-output queued (CIOQ) packet switches. As a result, a number of switch control algorithms have been proposed. Among these, scheduling policies based on maximum weight matching (MWM) were identified as optimal, in the sense that they were proved to achieve 100% throughput under any admissible arrival process satisfying the strong law of large number. On the contrary, it has been shown that the usual MWM policies fail to guarantee 100% throughput in networks of interconnected IQ/CIOQ switches. Hence, new policies suited for networks of interconnected switches were proposed and proved to achieve 100% throughput. All of these new policies require coordination and cooperation among different switches. We identify scheduling policies that require no coordination among switches (and are, thus, said to be local), and that guarantee 100% throughput in a network of IQ/CIOQ switches. The only assumptions on the input traffic pattern are that it is stationary, satisfies the strong law of large numbers and does not oversubscribe any link in the network.     

The bypass queue in fast packet switching

The telecommunications networks of the future are likely to be packet switched networks consisting of wide bandwidth optical fiber transmission media, and large, highly parallel, self-routing switches. Recent considerations of switch architectures have focused on internally nonblocking networks with packet buffering at the switch outputs. These have optimal throughput and delay performance. The author considers a switch architecture consisting of parallel plans of low-speed internally blocking switch networks, in conjunction with input and output buffering. This architecture is desirable from the viewpoint of modularity and hardware cost, especially for large switches. Although this architecture is suboptimal, the throughput shortfall may be overcome by adding extra switch planes. A form of input queuing called bypass queuing can improve the throughput of the switch and thereby reduce the number of switch planes required. An input port controller is described which distributes packets to all switch planes according to the bypass policy, while preserving packet order for virtual circuits. Some simulation results for switch throughput are presented     

Failure protection methods for optical meshed-ring communications networks

We study the survivability of a meshed-ring communication network that employs cross-connect switches. For WDM networks, the cross-connect switches are implemented as wavelength routers. Nodes can also provide cross-connection at the ATM VP (virtual path) level. By meshing the ring, the nodal degree of connectivity is increased as compared to a ring topology, and thus more alternative (protection) paths are available. For routing purposes, wavelength subnetworks are embedded in the topology. Nodes communicate with each other across one of the subnetworks to which both belong. We consider two types of subnetwork topologies to simplify the routing in a normal (nonfailure) situation. For each type of subnetwork, different protection methods are proposed to protect against a single link and/or nodal failure. The throughput performance of such meshed-ring networks under failure conditions is clearly superior to that achieved by (SONET) ring networks. We show that certain protection methods even result in lower values of the protection capacity as well as the protection capacity ratio (i.e., the overall capacity used under a failure divided by the total capacity) as compared to ring networks. We also present methods for constructing wavelength subnetworks to achieve single-failure protection using the minimal number of wavelengths.     

Multicast contention resolution with single-cycle windowing usingcontent addressable FIFO's

Asynchronous transfer mode (ATM) has been designated as the switching environment for future broadband integrated services digital networks (BISDN) networks and services. Although input-buffered space switches are more economical and simpler to implement than output-buffered space switches, they suffer from external blocking because of destination port contention. We review contention resolution methods used to avoid external blocking, and choose a solution based on ring reservation, resulting in an elegant and efficient mechanism requiring only nearest-neighbor communications. In addition to external blocking, space switches suffer from head-of-line (HOL) blocking, and our technique alleviates HOL blocking without arbitration time overhead. This method makes use of a novel content addressable first in/first out (CAFIFO) to achieve single-cycle windowing, and the CAFIFO design and operation are described in detail. High multicast throughput is achieved by employing call-splitting. Multiple latency priorities can also be supported. Simulation results, for both unicast and multicast switching, and both random and bursty traffic, highlight the versatility and excellent performance of the CAFIFO-based switch     

Performance issues in public ABR service

The available bit rate (ABR) service attracted much attention during the negotiations leading to Traffic Management Specification Version 4.0, finalized by the ATM Forum. In thr ABR service, feedback flow control of the source rate is provided in response to the changing asynchronous transfer mode (ATM)-layer transfer characteristics. The reference behavior of the source end system, the destination end system, and the switch, as detailed in the specification, allows cooperative control among these systems. The performance of the public ABR service is discussed in connection with the evolution of ATM switches. Public networks with first-generation switches provide an ABR service with a limited peak cell rate (PCR), while those with second-generation switches can provide an ABR service with any PCR. In such networks, TCP-over-ABR works well. Point-to-multipoint ABR will be provided in advanced switches. A method is proposed for maintaining the throughput of point-to-multipoint ABR when the number of leaves is increased     

High-speed CMOS switch designs for free-space optoelectronic MIN's

We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a two-dimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-μm CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 μm CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm² and a total power consumption (optics plus electronics) of about 90 W     

Hop-count fairness-aware protocols for improved bandwidth utilization in WDM burst-switched networks

In this paper, we propose and evaluate two schemes for improving bandwidth utilization in optical burst-switched (OBS) networks employing timer-based burst assembly routines. The first scheme adjusts the size of the search space for a free wavelength in optical switches using a balancing formula that promotes throughput and hop-count fairness. The formula achieves controllable increase in the size of the search space either when the size of the burst increases or when the hop count of the traveling burst increases. The second scheme proactively discards bursts at the source network access station using a dropping probability matrix that satisfies certain horizontal and vertical constraints. The matrix assigns smaller dropping probabilities to bursts with larger sizes and longer lightpaths. The results of extensive performance tests to evaluate the two schemes and compare them with previous schemes for improving fairness and throughput are presented and discussed. The results show that the two schemes improve the throughput of optical OBS networks and enhance the hop-count fairness.     

Accurate modelling of the queueing behaviour of shared buffer ATM switches

A model for the analysis of multistage switches based on shared buffer switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared buffer switches do not suffer from the head of line blocking which is the common problem in simple input buffering. The analysis models the state of the entire switch and extends the model introduced by Turner to global flow control with backpressure mechanism. It is shown that buffer utilization is better and throughput improves significantly compared with the same switch using local flow control policy. Copyright © 1999 John Wiley & Sons, Ltd.     

An efficient contention resolution algorithm for input queuing atm cross-connect switches

This paper describes an efficient contention resolution algorithm and its distributed implementation for large capacity input queuing cross-connect switches, which will establish virtual paths in future broadband ATM networks. The algorithm dynamically allocates sending time to cells held in input queues when no contention is indicated in the designated output ports. An expression for the mean delay and the cell loss probability for random traffic are derived through an approximate analysis. Input cells are served on a first-come, first-served basis as conventional contention resolution algorithms whose throughput saturates at 58 per cent because of head of line blocking in input queues. The proposed algorithm achieves a maximum throughput of 76 per cent.     

在基于MPLS的ATM交换机上RIO算法实现的研究

如何提高Internet网上的服务质量是目前研究的热点。本文研究了在基于多协议标签交换机制的ATM交换机上支持区分服务业务类型的一种实现算法。通过对该算法的通过率、公平性和时延等性能的研究表明:RIO算法能够较好地支持区分服务的业务类型。     

Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch

As an alternative to input-buffered switches, combined input-crosspoint buffered switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin (RR) arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distributions, only weight-based selection schemes are reported to provide high throughput. We propose an RR based arbitration scheme for a combined input-crosspoint buffered packet switch that provides nearly 100% throughput for several admissible traffic patterns, including uniform and unbalanced traffic, using one-cell crosspoint buffers. The presented scheme uses adaptable-size frames, so that the frame size adapts to the traffic pattern.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

Link-State-Based Algorithms for Dynamic Routing in All-Optical Networks with Ring Topologies

The increased usage of large bandwidth in optical networks raises the problems of efficient routing to allow these networks to deliver fast data transmission with low blocking probabilities. Due to limited optical buffering in optical switches and constraints of high switching speeds, data transmitted over optical networks must be routed without waiting queues along a path from source to destination. Moreover, in optical networks deprived of wavelength converters, it is necessary for each established path to transfer data from source to destination by using only one wavelength. To solve this NP-hard problem, many algorithms have been proposed for dynamic optical routing like Fixed-Paths Least Congested (FPLC) routing or Least Loaded Path Routing (LLR). This paper proposes two heuristic algorithms based on former algorithms to improve network throughput and reduce blocking probabilities of data transmitted in all-optical networks with regard to connection costs. We also introduce new criteria to estimate network congestion and choose better routing paths. Experimental results in ring networks show that both new algorithms achieve promising performance.     

On multicast support for shared-memory-based ATM switcharchitecture

Because of its superior performance characteristics in terms of cell loss and throughput for a given memory space, shared-memory ATM switches have gained significant importance in handling bursty traffic in ATM networks. Because of its increased effective load, multicast traffic requires an even greater increase in switching capacity than a shared-memory-based ATM switching system can provide. In order to support multicast operations with a memory-based switching system, the replication and storage methods used for multicast ATM cells for switching purposes become important. Various ways used to support multicast operation with a shared-memory-based ATM switching system have been categorized into several classes. Performance evaluation shows that the class of single-write single-read multicast scheme with output mask (CSWSR-w-OM) implementation overcomes the memory bottleneck involved with replication of multicast cells. It also provides superior performance for a given memory space employed in the shared-memory switching system in comparison to other classes of multicast schemes     

The sliding-window packet switch: a new class of packet switch architecture with plural memory modules and decentralized control

Shared-memory based packet switches are known to provide the best possible throughput performance for bursty data traffic in high-speed packet networks and internets compared with other buffering strategies under conditions of identical memory resources deployed in the switch. However, scaling of shared-memory packet switches to a larger size has been restricted mainly due to the physical limitations imposed by the memory-access speed and the centralized control for switching functions in shared-memory switches. A new scalable architecture for a shared-memory packet switch, called the sliding-window (SW) switch, is proposed to overcome these limitations. The SW switch introduces a new class of switching architecture, where physically separate multiple memory modules are logically shared among all the ports of the switch, and the control is decentralized. The SW switch alleviates the bottleneck caused by the centralized control of switching functions in large shared-memory switches. Decentralized switching functions enable the SW switch to operate in a pipeline fashion to enhance scalability and switching capacity compared with that of previously known classes of shared-memory switch architecture.     

A Performance Analysis of TMN Systems Using Models of Networks of Queues,Jackson's Theorem,and Simulation

We analyze the performance of a telecommunications management network (TMN) system using models of networks of queues, Jackson's theorem, and simulation. TMN systems for managing public asynchronous transfer mode (ATM) networks generally have a four‐level hierarchical structure consisting of a network management system, a few element management systems (EMSs), and several pairs of agents and ATM switches. We construct a Jackson's queuing network and present formulae to calculate its performance measures: distributions of queue lengths and waiting times, mean message response time, and maximum throughput. We perform a numerical analysis and a simulation analysis and compare the results.     

Optical CDMA for All-Optical Sub-Wavelength Switching in Core GMPLS Networks

Generalized multi-protocol label switching (GMPLS) is a multipurpose control-plane paradigm that extends the MPLS scheme allowing switching without recognizing packet boundaries. In this paper, we present a novel extension that exploits a new physical layer for switching in optical GMPLS. The proposed extension is achieved through adding an optical code switching layer, or code switch capable (CSC) layer, to the existing label mapping layers. Our proposal enables finer granularity at sub-wavelength level in all-optical GMPLS core switches, resulting in significant enhancements to traffic isolation capabilities for all-optical GMPLS core switches. We employ mathematical analysis to derive performance bounds for the proposed scheme, from both the labeling capacity and network throughput points of view. We use our analytical model to derive several optimum operating points for the network, and show that our techniques significantly improve the overall performance of all-optical core networks     

NN based ATM cell scheduling with queue length-based priorityscheme

The asynchronous transfer mode (ATM) is the choice of transport mode for broadband integrated service digital networks (B-ISDNs). We propose a window-based contention resolution algorithm to achieve higher throughput for nonblocking switches in ATM environments. In a nonblocking switch with input queues, significant loss of throughput can occur due to head-of-line (HOL) blocking when first-in first-out (FIFO) queueing is employed. To resolve this problem, we employ bypass queueing and present a cell scheduling algorithm which maximizes the switch throughput. We also employ a queue length based priority scheme to reduce the cell delay variations and cell loss probabilities. With the employed priority scheme, the variance of cell delay is also significantly reduced under nonuniform traffic, resulting in lower cell loss rates (CLRs) at a given buffer size. As the cell scheduling controller, we propose a neural network (NN) model which uses a high degree of parallelism. Due to higher switch throughput achieved with our cell scheduling, the cell loss probabilities and the buffer sizes necessary to guarantee a given CLR become smaller than those of other approaches based on sequential input window scheduling or output queueing     

High performance real-time neural scheduler for ATM switches

Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time     

Congestion control in asynchronous, high-speed wormhole routingnetworks

High-speed networks use lightweight protocols and a simple switch architecture for achieving higher speeds. A lightweight switching technique for local area and campus environments is wormhole routing, in which the head of a packet (worm), upon arriving at an intermediate switch, is immediately forwarded to the next switch on the path. Thus, the packet, like a worm, may stretch across several intermediate switches and links. Wormhole routing networks provide low latency. However, they are particularly prone to congestion, thus requiring careful flow control. The authors consider high-speed, asynchronous, unslotted wormhole routing networks. For such networks, two different flow control mechanisms are compared and contrasted, namely, backpressure flow control and deflection routing (with local input rate control). With backpressure, in order to maintain deadlock-free routing, either up/down routing or shortest path routing with virtual channels is assumed. With deflection routing, to avoid livelocks, worm alignment (delayed deflection) is performed at the switches. It is shown via simulation that the throughput performance of the two schemes is comparable (except for up/down routing). The authors also discuss the tradeoffs with respect to the complexity of hardware, routing protocols and buffer requirements. The authors further examine the role of input rate control at the hosts to overcome unbounded delays typical of deflection routing, and show it is possible to achieve lower average number of hops and transit delays by employing suitable input rate control policies