Micropower circuits for bidirectional wireless telemetry in neural recording applications

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.     

A New Extraction Technique for the Complete Small-Signal Equivalent-Circuit Model of InGaP/GaAs HBT Including Base Contact Impedance and AC Current Crowding Effect

In this paper, both ac current crowding and base contact impedance are considered and included in the T-type small-signal equivalent circuit of InGaP/GaAs heterojunction bipolar transistors. The ac current crowding effect and base contact impedance are modeled as a parallel$RC$circuit, respectively. Devices parameters of the equivalent circuit are obtained by a new parameters extraction technique. The technique is to directly analyze the two-port parameters of multibias conditions (cutoff-bias, open-collector, and active-bias modes). The parallel capacitances ($C_B$and$C_ bi$), base resistances ($R_B$and$R_ bi$), and base inductance$(L_B)$are especially determined under the active-bias mode without numerical optimization. In addition, the small-signal equivalent circuits of cutoff-bias and open-collector modes are directly derived from the active-bias mode circuit for consistency. By considering base contact impedance and intrinsic base impedance effects in the presented small-signal equivalent circuit, the calculated$S$-parameters agree well with the measured$S$-parameters. The observed difference in the slope for the unilateral power gain$(U)$versus frequency at high frequency is mainly attributed to the ac emitter current crowding effect and well modeled in this study.     

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-$mu$ m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11$times$ boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.      

A fully integrated low-noise 1-GHz frequency synthesizer design formobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm², the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter     

A low-output-impedance fully differential op amp with large outputswing and continuous-time common-mode feedback

A fully differential (zero common-mode voltage) op amp has been developed which has low output impedance, but unlike source-follower output stages, it has a large output swing, namely, 8 V_p-p for 1-kΩ load and a 5-V supply. The output stage, which is a combination of common-source and source-follower stages, is driven by the two complimentary outputs of the differential-output input stage. A continuous-time common-mode feedback circuit has been used, which due to the op amp's low output impedance, causes negligible open-loop gain (95 dB) degradation. Floating compensation capacitors are used in order to reduce the capacitance value and, hence, the area (490 mil²)     

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-$muhbox{m}$ CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.      

Equipartition laws of thermal noise

Classically, the thermal noise in electricalRCcircuits andLCRseries circuits is governed by the equipartition lawfrac{1}{2}overline{CV^{2}} = frac{1}{2}kT, whereV(t)is the noise voltage developed acrossC. When quantum effects are taken into account, the equipartition law no longer holds forRCcircuits, although an equipartition law can be deemed for the measured mean square noise voltage under certain conditions. InLCRseries circuits the equipartition lawfrac{1}{2}overline{CV^{2}} = frac{1}{2}kT, changes intofrac{1}{2}overline{CV^{2}} = frac{1}{2}bar{E}(f_{0})for high-Qtuned circuits, wherebar{E}(f_{0})is the average energy of a harmonic oscillator tuned at the tuning frequency of the tuned circuit.     

The minimization of parasitics in integrated circuits by dielectric isolation

A radically new technique for the fabrication of integrated circuits which completely changes microelectronic design is described. In place of the back-biased pn junctions usually used for isolation of devices in a substrate, a dielectric is substituted whose properties are such that almost total isolation is achieved with no increase in area. Leakage currents are reduced by several orders of magnitude to around 10^-10amperes/cm², stray capacitances to around 10^-5pf/µ², parasitic npnp and pnpn action is eliminated, and breakdown voltage is increased up to 1000 volts. Great flexibility in the design of components is achieved through the ability to place highly conductive "wells" where needed to obtain the benefits of epitaxial techniques, and by the ability to use devices having higher breakdown voltages. The technique makes practically all circuit configurations possible, and greatly enhances the possibilities for fabrication of npn and pnp transistors in the same substrate. Some details on circuits fabricated by this technique are given, such as digital circuits with propagation delay times of 3 nanoseconds and a video amplifier with a gain-bandwidth product of over 700 Mc.     

A process for the combined fabrication of ion sensors and CMOScircuits

A novel process for the fabrication of ion-selective field-effect transistors (ISFETs) together with CMOS circuits on the same chip is reported. The process is based on a standard 2-μm, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFETs are fabricated with floating polysilicon gates, which are exposed to photolithographic masking and HF etching before silicon nitride is deposited on the wafer. This layer of Si₃N₄ acts both as the pH-sensitive insulator for the ISFETs and as a protection layer for the on-chip circuitry buried beneath it. A source-follower circuit is described that provides an output voltage dependent on the threshold-voltage variations of the sensing transistor     

Experimental method to extract AC collector-base resistance fromSiGe HBT's

A simple experimental technique is presented that enables the accurate extraction of the collector-base resistance r_μ that models the impact of neutral base recombination on the ac output resistance of bipolar transistors. Measurements of ratios of r_μ to the output resistance r_o arising from the Early effect for SiGe HBTs allows for the quantitative determination of the impact of neutral base recombination on analog circuits that are designed to have a high output resistance. It is found that SiGe HBT structures indicative of those currently being used commercially in advanced analog processes exhibit neutral base recombination that is significant enough to severely degrade the output resistance of analog circuits, even when the output transistors experience ac base voltage drive conditions. Finally, it is shown how extraction of the ratio of r _μ to r_o can be a useful tool to determine the impact of parasitic potential barriers formed by boron out-diffusion at the collector-base junction on device and analog circuit performance     

An 8b 250MS/s 0.13μm CMOS ADC using variable references for VGA-to-WUXGA scaler chips

This work proposes an 8b 250MS/s 0.13??m CMOS two-step pipeline ADC using variable references for VGA-to-WUXGA scaler chip applications. The input sample-and-hold amplifier employs MOS capacitor-based gate-bootstrapping circuits to keep the on-resistance of sampling switches constant and to sample wide-band wide-range variable inputs with least distortion. The capacitors of the proposed multiplying D/A converter are laid out in a high matching one-dimensional symmetric shape rather than the conventional common-centroid topology to save chip area. The proposed on-chip current and voltage reference circuits generate variable bottom-side reference voltages with a fixed top-side reference using a single external voltage for processing wide-range variable analog inputs. The two-step reference selection scheme reduces considerably power and area in the last-stage 5b flash ADC. The prototype ADC in a 0.13??m CMOS demonstrates measured differential and integral non-linearities within 0.35 and 0.54 LSB, respectively. The ADC shows a maximum SNDR and SFDR of 44.4 and 56.1?dB at 250?MS/s, respectively. The ADC with an active die area of 0.72?mm² consumes 58.8?C62.4?mW depending on input modes at 250?MS/s and 1.2?V.     

电容电感测试仪的设计

介绍了电容电感测试仪的测量原理和电路设计方法,采用STC89C51单片机作为计算核心,以LC三点式振荡电路作为测量电路,采用固定的电感和电容组成LC振荡电路。单片机负责控制频率的测量,并利用单片机设计频率计测量得到分频后的频率,运用谐振频率公式,间接得到待测的电容值或电感值。该方案进行电容和电感的测试,具有电路原理简单、体积较小的优点。     

开关型DC-DC控制芯片片上软启动电路设计

针对传统开关型DC-DC:控制芯片软启动电路需使用片外电容,且难以实现全片上集成的缺点,提出一种全数字方式实现的片上软启动电路,可实现软启动功能的全片上集成.集成了该电路的控制芯片具有启动平稳、对启动瞬间的电压过冲和电流浪涌具有良好抑制功能等特点.由于减少了芯片的引脚和省去了片外电容,还有利于缩小整机体积,降低系统设计...     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface

As FPGAs integrate into high-speed systems, performance and signal integrity become more important in I/O design. This paper describes the development of an FPGA design to support 1.6 Gb/s differential source-synchronous standards and 300 MHz external memory interfaces. Speed and performance were achieved using circuits such as differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. Programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3-V voltage tolerance are features of the I/O buffer. In addition, DLLs and programmable phase-offset circuits were used to obtain precise timing control. The chip was manufactured on a 90-nm CMOS process.     

Profiling of optically active defects

A new method for profiling of optically active defects is presented. Traps in a depletion region are illuminated with chopped extrinsic light(hnu < E_{g}). The resulting ac photocurrent in the external circuit originates from a small part of the depleted layer. The trap profile is obtained by changing the bias voltage which moves the active traps with respect to the semiconductor surface. The method is illustrated with measurements made on an MOS tunnel device.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Design for testability and DC test of switched-capacitor circuits

The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacitors are represented in a simple form. Then, the transfer function becomes a product of the ratio of two capacitors and the sensibility of the DC gain to each capacitor is close to unity. Consequently, a simple test with partial diagnosis is realised with some DC voltage stimuli and gives an accurate test result at the output of the last voltage amplifier     

Multiple-Mode OTA-C Universal Biquad Filters

Two new multiple-mode (including voltage, current, transconductance, and transresistance modes) OTA-C universal biquad filters are proposed. The first proposed circuit uses only four operational transconductance amplifiers (OTAs) and two grounded capacitors. The second proposed circuit uses five OTAs and two grounded capacitors. Both the proposed circuits can realize voltage, current, transconductance, and transresistance mode universal filtering responses (low-pass, high-pass, band-pass, notch, and all-pass) from the same topology. The first proposed circuit uses the least number of components. This represents an attractive feature from a chip area and power consumption point of view. The second proposed circuit has no need of extra inverting and non-inverting amplifiers for special input signals. Moreover, both the proposed biquads still have (i) the employment of two grounded capacitors, (ii) cascadable connection of the former voltage-mode stage and the latter current-mode stage, and (iii) low sensitivity performance. H-SPICE simulation results confirm the theoretical analysis.     

智能燃油液位计的设计

燃油液位计是发动机燃油保障系统的一个重要装置,它的功能是准确地测量油箱的剩余油量以维持对发动机的自动供油,使发动机能够正常的运行。本文介绍了电容式液位传感器的基本原理和电容检测芯片PS？21的测量原理,设计了液位计系统的软硬件,同时传感器结构的设计考虑到了液位传感器的边缘效应,电路大大减弱了寄生电容杂散电容的影响,并实...