源端射频干扰下CMOS数字电路的时序失效机理

当前CMOS数字芯片设计流程缺少对电路电磁抗扰性的检验。大幅电磁干扰会导致数字电路出现电路失效,但电路失效的原因以及电路失效与幅度和频率等干扰参数的关系尚不清楚。针对这一问题,详细研究了源端射频干扰下CMOS数字电路的工作状态。通过给出失效与干扰参数的关系的基本理论,得到CMOS数字电路在受扰情况下的失效原因。结果表明,时序错误是大幅电磁干扰引起CMOS电路失效的主要原因。电路失效可通过电路路径延时的漂移和抖动来解释,漂移和抖动与电磁干扰的幅度和频率存在特定关系,因此时序失效是可预测的。基本理论所描述的失效规律可作为EDA工具的原理,用于芯片设计早期阶段对电路的抗扰性检验。     

一种无需振荡器的数字频率抖动电路及其应用

为了解决滞环控制模式开关电源中无振荡器电路,从而无法使用现有频率抖动方式降低EMI和现有频率抖动电路调制方式单一、移植性差的问题,本文提出了一种新型的数字频率抖动电路,该电路结构简单,调制方式多样,可移植性好。本设计采用1μm 40V CMOS工艺进行仿真验证,Hspice仿真结果表明该数字频率抖动电路有效地降低了系统的EMI。     

电缆测井深度测量电路的抗干扰设计

针对电缆测井作业过程中电磁干扰和电缆抖动对电缆测井深度系统的影响,本文介绍了采用增量式光电编码器的深度测量电路的工作原理,详细分析了电磁干扰和电缆抖动等因素带来深度测量误差的机理,并在此基础上提出了新的抗干扰电路设计,该设计已应用在国内外许多油田的电缆测井现场,在深度系统抗干扰和防电缆抖动方面取得了良好的应用效果。     

A 1.5 GHz All-Digital Spread-Spectrum Clock Generator

An all-digital spread-spectrum clock generator (SSCG) has been fabricated in a 0.18 $mu{hbox {m}}$ CMOS process. The analysis and design of this all-digital SSCG is presented. A mixed-signal phase and frequency detector is adopted to reduce the jitter, eliminate a digital adder, and also reduce latency. A Vernier time-to-digital converter (TDC) with time amplifiers is realized to enhance the timing resolution of the TDC and to track the frequency modulation in the SSCG. A digitally controlled oscillator with a resolution enhancement circuit is also presented. The measured electromagnetic interference reduction is 10.48 dB. The measured peak-to-peak jitter and rms jitter are 28.4 ps and 4$~$ps, respectively, at 1.5 GHz.      

数字逻辑电路GPIO电磁抗扰度的热应力效应分析

针对集成电路（integrate circuit,IC）在复杂环境中的电磁抗扰度漂移问题,研究了环境热应力对典型数字逻辑集成电路通用输入/输出（general purpose input output,GPIO）端口电磁抗扰度的影响.分析典型FPGA GPIO电气拓扑结构及电磁-热耦合应力对其内部金属氧化物（metal-oxide-semiconductor,MOS）敏感器件的干扰机理,基于集成电路电磁传导抗扰度模型（integrate circuit immunity model-conducted immunity,ICIM-CI）,将环境热应力干扰因素引入GPIO电磁抗扰预测分析中,建立传导抗扰度-热效应仿真预测模型（ICIM-CI-temperature,ICIM-CI-T）,设计基于电磁干扰直接功率注入（direct power injection,DPI）与热应力耦合的抗扰度测试平台,仿真与测试得到了对应的抗扰度阈值变化曲线.结果表明,在10 MHz~1 GHz频率范围内,模型仿真与测试结果一致性好.在环境热应力从20℃变化到100℃过程中,当频率小于200 MHz时,GPIO电磁抗扰度基本不受热应力影响;在200~700 MHz频段内,GPIO电磁抗扰度随着热应力干扰的增加而降低,其中300 MHz和600 MHz频点处的抗扰度阈值下降4 dBmw,也是该FPGA需要重点防护的频段.     

On the prediction of digital circuit susceptibility to radiated EMI

The effects of radiated radio-frequency interference (RFI) on the operation of digital systems are studied by simulating the response of simple logic circuits to incident plane waves. The simulation is accomplished by combining a linear electromagnetic moment-method model of the wire structure with a nonlinear circuit model of the solid-state components. The complete model is analyzed in the linear and nonlinear regimes as an example. It is shown how a circuit simulator, such as SPICE, can be used in the analysis of an arbitrary wire network loaded with logic circuits, by the process of representing the linear wire network as a lumped-element N-port π network and interfacing it to the nonlinear circuit simulator. Examples are given that demonstrate the occurrence of both static and dynamic failures under various RFI-field excitations and wire structure geometries. The prediction methods presented in this paper, can be used by EMC engineers to assess the likelihood of failures in RFI-exposed digital systems,     

EMI-induced failures in crystal oscillators

An electromagnetic interference (EMI) induced failure mode pertaining to crystal-based voltage-controlled oscillators (VCO) has been studied. The failure consists of a transition to a frequency of oscillation that differs from the crystal's fundamental resonant frequency, when the circuit is temporarily exposed to continuous or pulsed radio-frequency electromagnetic fields. The new state persists even after the EMI source is removed and leads to hang-up in digital systems. This mode transition has been observed experimentally. Its essential properties have been predicted theoretically and simulated numerically, using simplified oscillator models. The likelihood of observing such a failure in a noisy electromagnetic environment is assessed with respect to the radiated susceptibility levels given in MIL-STD-461B     

Spread spectrum clock Generator with delay cell array to reduce electromagnetic interference

In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-/spl mu/m CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz.     

高速数字电路设计的电磁干扰控制技术

分析了电磁干扰的特点,阐述了抑制电磁干扰的几种有效的方法,探讨了高速数字电路在噪声抑制方面的设计原则,对于设计高速数字电路具有一定的指导作用。     

用于通信系统的干扰对消电路设计与实现

针对通信设备应用的复杂化和对在复杂电磁环境下工作的设备电磁兼容性提出的更高要求,通过分析对消技术的基本原理,提出了一种模拟电路和数字电路相结合的干扰对消技术,并研制出了基于该技术的干扰对消原理样机.对该样机的单机测试和系统联试结果表明,该对消技术具备点频干扰和噪声干扰的抑制能力,对消收敛时间小于100 ms,对消比大于43 dB,适合在窄带通信中应用并可推广到其他领域.该成果正逐步在实际工程中得到运用.     

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).     

基于CPCI结构变频器的电源设计

基于CPCI结构变频器若直接采用CPCI机箱内部的开关电源,存在较为严重的电磁干扰,为了消除此电磁干扰,文中通过分析基于CPCI结构变频器的电磁干扰源及切断干扰源的方法,设计了一种电源处理方式,通过实际电路的杂散指标测试,得出该处理方式可以有效地隔离数字电路与模拟电路间的电磁干扰,降低开关电源对变频器的干扰及其输出纹波.此外,本设计可以为其他接收机电源设计提供参考.     

复接系统定时的数字提取技术及其性能

本文介绍了复接系统中数字定时提取电路的原理和结构,分析了数字定时提取电路输出定时的抖动特性,包括抖动幅度和抖动频率。同时,本文还分析了数字定时提取在数字复接系统中的应用,以及其对复接系统性能的影响,并给出实验结果     

基于UCD9240的数字电源设计

针对传统的电源设计存在开关频率低、频率波动大、电磁干扰大、无法实时调节等问题。文中采用UCD9240控制芯片完成某项目硬件平台的数字电源方案,进行硬件电路和软件参数配置的设计,并将对理论计算与实际数值进行了比较,结果显示该设计方案能较好地满足设计要求。     

光学探测系统电磁屏蔽设计与应用

光学探测系统在高功率微波系统运行造成的强辐射、强电磁干扰环境下工作,HPM产生的强电磁脉冲会通过后门耦合的方式由探测器前端光学镜头进入内部的电路系统造成光学探测系统瞬间黑屏、图像抖动、器件毁坏等现象,通过采用光学玻璃金属丝夹层的方法研制光窗,在2.4 GHz±100 MHz频段内电磁屏蔽性能达到了65 dB,同时满足探测目标的光窗透过率的要求。经过应用后表明:加载了这种电磁屏蔽光窗的光学探测系统在HPM工作时图像稳定,未受到干扰。     

Electromagnetic Susceptibility Analysis on a Digital Pulse Width Modulator for SMPSs

In this paper, a digital pulse width modulator (DPWM) is analyzed from the point of view of susceptibility to radio-frequency interference (RFI). The chosen DPWM architecture is based on the hybrid delay-line/counter scheme commonly used in the digital control of switched-mode power supplies (SMPSs). This paper focuses on the DPWM performance degradation in the presence of electromagnetic interference (EMI), and for this purpose a DPWM with time resolution down to 350 ps has been designed and manufactured in a standard 0.35- $mu$m complementary metal–oxide semiconductor technology. Measurements and analytical analyses are presented for both EMI effects on the internal generated clock signal and on the PWM duty-cycle precision. The immunity degradation mechanisms are investigated by means of an analytical approach, demonstrating that the PWM susceptibility is more strictly related to its functional design rather than to the implemented topology. The effects of clock and duty-cycle jitter induced by RFIs are finally verified using a simulation model on a digitally controlled buck converter, highlighting the importance of such issue on steady-state performances of SMPSs.      

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with 'OR' logic for dual-modulus operation,the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process.The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.     

场路结合法分析设备电磁辐照效应

电子设备机壳内部往往会内置多层印制电路板,外界电磁干扰很可能通过设备的外接导线进入设备内部进而对电路板造成损坏。针对这种情况,采用全波分析法获得受干扰设备的相关参数,利用该参数建立等效源模型;等效电路法分析内部电路板上电路的电磁特性。通过全波分析法和等效电路法相结合的方式来分析外界电磁干扰进入设备内部时所造成的影响,为处于高频电磁干扰环境中的电路工作特性研究提供新思路和参考。     

All Digital Spread Spectrum Clock Generator for EMI Reduction

An effective solution to control electromagnetic interference in computing appliances such as DVD players or home theater systems is to apply modulation on the system clock. The presence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation of a spread spectrum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a modulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit enables a process and temperature independent operation. The circuit occupies 0.06 mm² in a 0.15-mum CMOS process and consumes 7.1 mW