Capacitance-voltage analysis of a high-k dielectric on silicon

正Device characteristics of TiO_2 gate dielectrics deposited by a sol-gel method and DC sputtering method on a P-type silicon wafer are reported.Metal-oxide-semiconductor capacitors with Al as the top electrode were fabricated to study the electrical properties of TiO_2 films.The films were physically characterized by using X-ray diffraction,a capacitor voltage measurement,scanning electron microscopy,and by spectroscopy ellipsometry.The XRD and DST-TG indicate the presence of an anatase TiO_2 phase in the film.Films deposited at higher temperatures showed better crystallinity.The dielectric constant calculated using the capacitance voltage measurement was found to be 18 and 73 for sputtering and sol-gel samples respectively.The refractive indices of the films were found to be 2.16 for sputtering and 2.42 for sol-gel samples.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

Structural and interfacial properties of high-k HfOxNy gate dielectric films

The thermal stability and interfacial characteristics for hafnium oxynitride (HfO_xN_y) gate dielectrics formed on Si (1 0 0) by plasma oxidation of sputtered HfN films have been investigated. X-ray diffraction results show that the crystallization temperature of nitrogen-incorporated HfO₂ films increases compared to HfO₂ films. Analyses by X-ray photoelectron spectroscopy confirm the nitrogen incorporation in the as-deposited sample and nitrogen substitution by oxygen in the annealed species. Results of FTIR characterization indicate that the growth of the interfacial SiO₂ layer is suppressed in HfO_xN_y films compared to HfO₂ films annealed in N₂ ambient. The growth mechanism of the interfacial layer is discussed in detail.     

CH3NH3PbI3/p-Si异质结的光电特性研究

利用一步溶液法在p型Si衬底上生长有机/无机杂化钙钛矿CH3NH3PbI3薄膜,构成CH3NH3PbI3/p-Si异质结。利用原子力显微镜(AFM)、扫描电子显微镜(SEM)对薄膜形貌和结构进行表征,通过无光照和有光照条件下的电流-电压(I-V)、电容-电压(C-V)测试对异质结的光电特性进行研究。I-V测试结果显示CH3NH3PbI3/p-Si异质结具有整流特性,正反偏压为±5V时,整流比大于70,并在此异质结上观察到了光电转换现象,开路电压为10mV,短路电流为0.16uA。C-V测试结果显示Ag/CH3NH3PbI3/p-Si异质结具有与MIS(金属-绝缘层-半导体)结构相似的C-V特性曲线,与理想MIS的C-V特性曲线相比,异质结的C-V曲线整体沿电压轴向正电压方向平移。C-V特性曲线的这种平移表明Ag/CH3NH3PbI3/p-Si异质结界面存在界面缺陷,CH3NH3PbI3层也可能存在固定电荷。这种界面缺陷是导致CH3NH3PbI3/p-Si异质结开路电压的大幅度降低的重要原因。此外,CH3NH3PbI3薄膜的C-V测试结果显示其具有介电非线性特性,其介电常数约为4.64。     

直流磁控溅射制备非晶硅薄膜的研究

非晶硅薄膜（a-Si）是目前重要的光敏材料,在很多领域得到广泛应用。直流磁控溅射具有工艺简单．沉积温度低等优点,是制备薄膜的一种重要技术。采用直流磁控溅射工艺在玻璃基板上沉积薄膜,并对样品进行了退火处理。研究了沉积速率与溅射功率的关系。结果表明薄膜的沉积速率与溅射功率近似有线性关系。利用X射线衍射（XRD）对薄膜进行了分析鉴定,结果表明溅射的薄膜是非晶硅薄膜。利用扫描电子显微镜（SEM）对非晶硅薄膜的表面形貌进行了观察和分析,与X射线衍射测试的结果一致。所以．利用直流磁控溅射工艺能在常温下能快速制备出良好的非晶硅薄膜。     

Local crystal structural modifications in pulsed laser deposited high-k dielectric thin films on silicon and germanium

The thin film growth conditions are correlated with the local structures formed in Hf_xZr_1−xO₂ (x=0.0–1.0) high-k dielectric thin films on Si and Ge substrates during deposition. Pulsed laser deposition (PLD) technique has been used in the synthesis of the thin films with systematic variations of substrate temperature, Zr content of the targets and substrate selection. The local structural information acquired from extended X-ray absorption spectroscopy (EXAFS) is correlated with the thin film growth conditions. The response of the local structure around Hf and Zr atoms to growth parameters was investigated by EXAFS experiments performed at the National Synchrotron Light Source of Brookhaven National Laboratory. The competing crystal phases of oxides of Hf were identified and the intricate relation between the stabilized phase and the parameters as: the substrate temperature; Hf to Zr ratio; have been revealed. Specifically, HfO₂ thin films on Si(1 0 0) exhibit a tetragonal to monoclinic phase transformation upon increase in the substrate temperature during deposition whereas, HfO₂ PLD films on Ge(1 0 0) substrates remain in tetragonal symmetry regardless of the substrate temperature.     

利用同步晶化法制备的镍纳米晶的电荷存储特性

快速退火纳米晶化法是目前常用的金属纳米晶制备方法,但其后续600~900℃高温退火会降低器件的电学特性和可靠性。本文提出了热预算低的金属纳米晶制备的新方法—沉积过程中的同步金属薄膜原位纳米晶化法,可以省掉后续单独的退火处理工艺,使金属薄膜同步产生纳米晶化,降低工艺热功耗及简化工艺,从而有效地改善上述薄膜沉积后退火纳米晶化法的不足。在不同衬底温度（250~325 ?C）下,利用同步纳米晶化法制备镍纳米晶存储器。随着生长温度的增加,其存储窗口先增加到最大值再降低。衬底温度为300 ?C时,其存储窗口（2.78 V）最大。与快速热退火法镍纳米晶存储器相比较,同步纳米晶化法制备镍纳米晶存储器具有更强的电荷存储能力。另外,研究了不同操作电压和脉冲时间下器件的平带电压偏移量,当操作电压增加到±10 V时出现了较大的平带电压偏移量,这表明器件发生了大量的载流子（电子和空穴）注入现象。最后,模拟了金属纳米晶存储器的载流子（电子和空穴）注入和释放过程。     

溅射压力对制备a-GaAs1-xNx 薄膜光学常数的影响

采用反应磁控溅射法在室温条件下制备了a-GaAs_1-xN_x 薄膜。实验测定了薄膜厚度、氮含量、载流子浓度和光学透过率及并研究了其随溅射压的变化。系统研究了溅射压对所制备薄膜的光学带隙、折射率和色散参数的影响。所制备的薄膜为直接带隙材料,利用Cauchy和Wemple模型能够很好地拟合所制备薄膜的折射率色散曲线。     

Capacitance-voltage profiling and thermal evolution of the conduction band-offset of unstrained Ga0.47In0.53As/InP single quantum well

We report the results of capacitance-voltage (C-V) and Deep Level Transient Spectroscopy (DLTS) measurements performed upon a Ga_0.47In_0.53As/InP quantum well structure. At room temperature, a conduction-band offset ΔE_c=(200±10)meV and charge densities σ_I=±(3±1)*10¹¹ times the electronic charge per cm² have been measured from C-V experiments. At lower temperature (T≤150K) we have observed an important decrease of the band-offset, considerably larger than a pure thermal effect. We have shown that the explanation lies in the presence of a high concentration of deep traps located at the well-barrier interfaces. Two species A and B have been detected through DLTS experiments with activation energies E_tA=90 meV and E_tB=195 meV, respectively. The filling of these trap levels at low temperature lowers the band offset from 200 to 120 meV, owing to band repulsion effects.     

Pt—WO3薄膜气敏传感器的气敏性能研究

用直流反应磁控溅射法制备了Pt-WO3气敏薄膜,进行了薄膜晶体结构和表面形貌的分析,研究了添加Pt对WO3电学和气敏特性的影响。实验证明:当Pt膜厚为4 nm时,WO3薄膜对气体的敏感特性得到改善,对φ(NO2)=5×10-6和φ(NH3)=10×10-6的工作温度均降低了50℃,灵敏度分别达到11.5和900,是纯WO3薄膜的2~3倍,且响应时间缩短。     

直流磁控反应溅射制备硅基AIN薄膜

采用直流磁控反应溅射法,在Si(100)和Pt/Ti/Si(100)上制备了AlN薄膜。用X-射线衍射(XRD)、电镜扫描(SEM)、原子力显微(AFM)对薄膜的晶向结构和表面形貌进行了分析,研究了不同工艺参数对薄膜择优取向的影响,分析了AlN晶粒生长的有关机理。制备出的AlN薄膜显示出较好的(002)面择优取向性,半高宽(FWHM)为0.35°～0.40°,折射率约为2.07。     

pMOSFET中栅控产生电流的衬底偏压影响研究

研究了pMOSFET中栅控产生电流(GD)的衬底偏压特性。衬底施加负偏压后,GD电流峰值变小;衬底加正向偏压后,GD电流峰值增大。这归因于衬底偏压VB调制了MOSFET的栅控产生电流中最大产生率,并求出了衬底偏压作用系数为0.3。考虑VB对漏PN结的作用,建立了包含衬底偏压的产生电流模型。基于该模型的深入分析,很好地解释了衬底负偏压比衬底正偏压对产生电流的影响大的实验结果。     

电子束辐照下的石墨烯上的原子层沉积Al2O3介质层

为了研究石墨烯与高k介质的结合,使用原子层沉积氧化铝在石墨衬底上。沉积前使用电子束辐照,观测到了氧化铝明显改善的形貌。归因于电子束辐照过程中的石墨层的无定形变化过程。     

小尺寸堆栈高k栅介质GaAs nMOSFET阈值电压模型

通过求解沟道的二维泊松方程,建立了小尺寸高k栅介质GaAs MOSFET的阈值电压模型．模型包括了短沟道效应、漏致势垒降低效应和量子效应．模拟结果与TCAD仿真结果符合较好,证实了模型的正确性和实用性．利用该模型,分析了堆栈高k栅介质结构及其物理参数对阈值电压漂移的影响以及阈值电压的温度特性．结果表明,堆栈栅介质结构能有效抑制边缘场和DIBL效应,改善MOSFET的阈值特性和温度特性;未考虑量子效应的模型过高估计了温度对阈值电压的影响。     

成膜与热处理参数对溅射沉积ITO 膜电性能的影响

采用了补氧直流磁控反应溅射工艺制备ITO膜，在不同基片加热温度和补氧流量下获得最低方块电阻值的最佳制备工艺。对制备的ITO薄膜进行了退火热处理，研究不同温度热处理后膜的方块阻值的变化。实验表明，对一定的基片加热温度，ITO膜的方块电阻与溅射气氛中的补氧流量有关，并存在一个最佳补氧的值，在该条件下制备ITO的方块电阻最小，在膜厚为40nm埃时仅有不到100Ω／□。影响溅射沉积ITO透明导电薄膜方阻的，除了溅射沉积时基片的烘烤温度和补氧流量外，还包括后期大气退火热处理的温度。     

Annealing of lead zirconate titanate (65/35) thin films for ultra large scale integration storage dielectric applications: Phase transformation and electrical characteristics

Thin film capacitors of Lead Zirconate Titanate (PZT, 400 nm) of Zr/Ti ratio 65/35, deposited by reactive dc-magnetron sputtering, with low leakage current and high charge storge density(’Q _c ) for use as capacitor dielectrics in ultra-large scale integration dynamic random access memory (ULSI DRAM) cells have been fabricated and studied. The equivalent SiO₂ thickness for the optimized film is 5.3å for the fresh film and 9.1å after 10¹⁰ unipolar stress cycles (0 to -3 V). The leakage current density is 1.32 × 10^-7A/cm² for 3 V operation which is equivalent to an effective SiO₂ field of 55 MV/ cm. X-ray diffraction analysis reveals that as-deposited films (T _dep . = 200? C) contain no detectable perovskite phase. Post-deposition annealing is therefore essential, and critical to the fabrication of high quality capacitors for memory applications. The pyrochlore-to-perovskite phase transformation, the evolution of the microstructure, composition and the presence of different phases in the film have been studied as a function of annealing conditions. There is a purely outward radial growth of the interphase boundary, resulting in the increase in the curved surface area of the cylindrical perovskite aggregates throughout the film thickness with increasing thermal budget. The increase in perovskite phase content with annealing time at a constant annealing temperature indicates that a diffusional phase transformation from the pyrochlore to cubic perovskite phase above the Curie temperature occurs as a first step in the formation of the ferroelectric perovskite phase. The variation of two important dielectric properties, charge storage density and leakage current density is reported as a function of the annealing time and temperature. Furthermore, the variation of the charge storage density due to unipolar dynamic electrical stress is studied. The total area under the large-frequency C-V curve (which is the total reversible polarization) increases under unipolar dynamic stress (0 to -3 V) after 10¹⁰ stress cycles. The degradation in charge storage density is found to be primarily due to an increase in remanent polarization caused by the shift in the hysteresis loop as a result of the reduction in the internal bias field under the influence of the unipolar dynamic stress.     

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a standard 0.6 μm CMOS technology and single 1.5 V supply, simulations show that the proposed transconductor futures a THD of −50 dB for 1.4 V_pp and 10 MHz input signal and −60 dB for 1.4 V_pp and 1 MHz signal where the threshold voltage of MOS transistors could be as high as 1 V. Based on the proposed transconductor, a lowpass filter with 700 kHz to 8 MHz programmable cutoff frequency and a bandpass 10.7 MHz second order filter were implemented. Armin Tajalli received the B.Sc. from Sharif University of Technology (SUT), Tehran, Iran, in 1997, and M.Sc. from Tehran Polytechnic University, Tehran, Iran, in 1999. From 1998 he has joint Emad Co. as a senior design engineer were he has worked on several industrial and R&D projects on analog and mixed-mode ICs. He received the award of the Best Design Engineer from Emad Co., 2001, the Kharazmi Award of Industrial Research and Development, Iran, 2002, and Presidential Award of the Best Iranian Researchers, in 2003. He is now working toward his PhD degree at SUT. His current interests are design of high speed circuits for telecommunication systems. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993. From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.     

硅基AlN薄膜制备技术与测试分析

采用直流磁控反应溅射法,在Si(100),Al/Si(100)和Pt/Ti/Si(100)等多种衬底上制备了用于MEMS器件的AlN薄膜．用XRD和AES对薄膜的结构和组分进行了分析,通过优化工艺参数,得到了提高薄膜择优取向的方法,并分析了不同衬底上AlN晶粒生长的有关机理．制备的AlN薄膜显示出良好的〈002〉择优取向性,摇摆曲线的半高宽达到5.6°．