Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

数字下变频器在软件无线电接收机中的应用

在软件无线电（Software Radio)接收机中，数字下变频器（Digital DownConverter-DDC)技术是其核心技术之一。数字下变频技术是将宽带大数据流信号变成窄带低数据流信号，以便DSP实时处理。文章指出，作为过渡阶段的软件无线电，用数字变频器实现中频段的处理任务。着重介绍了其主要功能，内部结构的抽取滤波的特性。最后，以Interial公司的可编程DDCHSP50214B为例，给出了软件无线电接收机的原理图。     

Ka-band direct digital receiver

A new direct-conversion wideband (26-28.5 GHz) six-port receiver is proposed for mass-market wireless communications. This six-port receiver is designed to operate without the need for precise power reading and the use of a digital signal processor that is usually required in other receivers. The proposed receiver architecture is chosen to satisfy requirements of hardware receivers used in high-speed QPSK communications. The receiver contains a receiver front-end, QPSK demodulator, and carrier recovery module. A reverse modulation loop was used to provide a rapid carrier recovery. The maximum bit rate is determined solely by the limiting speed of the baseband module. This new hardware receiver is proposed as a robust, rugged, low-cost receiver for use in wide Ka-band wireless mass-market QPSK communications such as local multipoint distribution system services, which is a prime example of communication equipment requiring such receivers. Bit-error-rate results are presented versus the noise and reference signal phase shift.     

A software radio architecture for linear multiuser detection

The integration of multimedia services over wireless channels calls for provision of variable quality of service (QoS) requirements. While radio resource management algorithms (such as power control and call admission control) can provide certain levels of variability in QoS, an alternate approach is to use reconfigurable radio architectures to provide diverse QoS guarantees. We outline a novel reconfigurable architecture for linear multiuser detection, thereby providing a wide range of bit error rate (BER) requirements amongst the constituent receivers of the reconfigurable architecture. Specifically, we focus on achieving this dynamic reconfiguration via a software radio implementation of linear multiuser receivers. Using a unified framework for achieving this reconfiguration, we partition functionality into two core technologies [field programmable gate arrays (FPGA) and digital signal processor (DSP) devices] based on processing speed requirements. We present experimental results on the performance and reconfigurability of the software radio architecture as well as the impact of fixed point arithmetic (due to hardware constraints)     

一种基于Costas环的BPSK解调设计

设计了一种基于软件无线电思想的中频数字化接收机系统,该系统由数据采集模块、数字下变频（DDC）模块和数字解调模块构成。文中重点研究了基于Costas环的BPSK相干解调,并介绍了载波同步及BPSK解调的工作流程图,最后通过Simulink对BPSK解调原理进行了仿真验证。     

A Software Defined Radio Platform with Direct Conversion: SOPRANO

In this paper, a new software defined radio platform with direct conversionisintroduced.The platform is named SOPRANO, which stands for Software Programmableand Hardware Reconfigurable Architecture for Network.Main features of SOPRANO include a high-level design methodologyfor digital circuits, direct conversion based on six-port technology, andnovel digital signal processingalgorithms for multi-band and multi-mode operation.The first prototype of the SOPRANO platform has been built and was ableto receive M-ary PSK (Phase Shift Keying)and QAM (Quadrature Amplitude Modulation) signals,with two different carrier frequencies at 2.45 GHz and 5.25 GHz,by changing signal-processing software.     

Signal processing challenges for applying software radio principles in future wireless terminals: an overview

The general idea of software radio is to develop highly integrated radio transceiver structures with high degree of flexibility and multimode capabilities, achieved through increased role of digital signal processing software in defining the functionalities which have traditionally been implemented with analog RF techniques. This paper explores the software radio concept from the receiver architecture and signal processing points of view, with mainly the wireless terminal application in mind. We first discuss the critical issues in alternative receiver architectures with simplified analog parts and increased configurability. We also introduce certain advanced digital signal processing techniques which could potentially relieve some of the essential problems and pave the way towards DSP‐based, highly integrated, and highly configurable terminals. Big emphasis is on efficient digital multirate signal processing methods and complex (I/Q) signal processing. Copyright © 2002 John Wiley & Sons, Ltd.     

Enabling Components for Multi-Standard Software Radio Base Stations

Receiver and transmitter technology is an enablingfactor for the software radio concept, with analogueto digital conversion being the limiting performancefactor. The requirement for common hardware forseveral different systems leads to parameterizedmodules and higher integration levels. Moduledefinition is closely related to the architecturalchallenges of receiver design. Emerging multi-mode base stations favour larger hardware granularity. Thesoftware radio approach reduces the hardwarecomplexity of a cell site from several racks ofdiscrete single-channel radios to one or two shelvesof open architecture modules.This paper presents critical functional blocks forwide-band multi-mode base stations based on thesoftware radio concept. Major component specificationsare reviewed showing the implications on systemdesign. Functional and performance parameters foranalogue to digital converters (ADCs), digital toanalogue converters (DACs), digital down and upconverters are illustrated using specific products.Applications are presented by revisiting existingtransceiver architectures in the framework of nextgeneration wireless standards.     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

基于ADS的无线接收机数模混合系统级仿真

采用自顶向下的方法，设计了工作于L波段的宽带无线接收机。该接收机采用数模混合的weaver结构。构造了接收机模拟前端和数字基带的各个功能模块，并用ADS(Advanced Design System)软件完成了接收链路的系统级混合信号仿真。     

RF Band‐Pass Sampling Frontend for Multiband Access CR/SDR Receiver

Radio frequency (RF) subsampling can be used by radio receivers to directly down‐convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog‐to‐digital converter (ADC) as near the antenna as possible. Based on this, a band‐pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second‐order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second‐order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second‐order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

软件无线电电台的计算机仿真

分析了软件无线电的分层结构,设计了一种软件无线电电台模型,其射频段参数、信道模型、调制方式和信源编码方式等可编程控制。建立了一种软件无线电电台的计算机仿真平台,进行了计算机仿真,验证了软件无线电的一些重要思想和技术。针对AM,SSB,FM,OOK,PSK,QPSK,MSK,FSK,16QAM九种信号,仿真结果表明,在载波频率、调制方式、信道模型等可以根据需要设置的环境下,电台的收发都能达到预期效果。当接收信号的信噪比为20 dB,AM与SSB调制度为0.8,FM的调频指数为3、数字调制的传速率都为2000 b/s时,载波频率的平均检测误差不大于2%,平均调制类型识别正确率不低于96%,模拟调制的平均失真率小于3%,数字调制的平均误码率小于10-5。     

宽带数字单边带下变频器

数字单边带下变频器是软件无线电中不可缺少的组成部分,也是射电观测中,数据采集设备的重要组成部分,由于该模块紧接高速A/D采样器之后,所以对其运算处理能力有很高的要求.本文提出了实现宽带数字单边带下变频器的一种可行方案——并行处理,可以从根本上解决数字信号处理的瓶颈效应.     

一种新型前馈自动增益控制光接收机的研究

自动增益控制模拟光接收机广泛应用于光纤有线电视、光纤直播卫星电视、无线通讯及雷达等射频微波信号光传输,是实现大动态范围光载波信号高质量接收必不可少的一项技术.我们采用一种入射光功率电平检测与处理的新方法,对模拟光接收机的增益进行控制,将接收机输出电平控制在要求的范围内,实现了一种新型的无射频反馈电路的自动增益控制光接收机.     

低成本直接射频正交调制无线发射机的新设计

提出了现场可编程门阵列(FPGA)直接射频正交调制无线通信发射机的一种新设计。新设计克服了传统正交调制方案结构复杂的缺点,去掉了传统正交调制方案中的基带数字处理芯片和射频部分之间的数模转换器件和混频器,使基带数字处理芯片和射频正交调制器直接连接,最大化地实现了传统无线通信发射机的软件化和数字化。采用新技术制作的无线发射系统的实测表明,新发射机误码率达到了传统的正交调制方案的误码水平。新设计不需要传统方案必须的数模转换器件和混频器,使系统简化,成本降低。     

全数字接收机的结构及关键技术

全数字接收机是近几年提出的新的接收机结构，它采用高稳定度晶体振荡器产生本地时钟用于解调及采样，载波相差和时钟寒时误差的消除，信号的判定等全部由数字信号处理器来完成，本文介绍了全数字接收机的体系结构，并对其实现的关键技术进行详细的讨论。     

Putting the "FLEX" in flexible mobile wireless radios - A wideband continuous-time baudpass sigma-delta ADC software radios

This article has provided a brief overview of the SigmaDelta ADC conversion technologies for SDRs. The wireless receiver challenges were identified, the ADC design considerations and SigmaDelta solutions were discussed, and a low-distortion CT BP SigmaDelta modulator architecture was presented. The article has shown that the proposed CT BP SigmaDelta modulator is suitable for implementing high-IF ADC, making possible the software radio in handhelds. The major challenges in implementing such a high-IF ADC are the power dissipation and the degree of configurability, programmability, and adaptability that can be achieved by applying digital tuning and adaptive calibration     

软件无线电在现代雷达中的应用

简要阐述软件无线电的起源，并结合雷达系统的各组成部分介绍了软件无线电技术在其中的应用，包括数字接收机、数字信号处理器、数字频率源、数字波形产生、智能天线，以及在现代雷达中的软件无线电技术发展和方向。     

全数字高速OQPSK信号解调技术分析

根据某侦察接收机的需要,基于软件无线电设计思想,分析了影响解调性能的主要因素以及解决方法,提出了一种偏移正交相移键控(OQPSK)解调器的全数字实现结构。介绍了数字下变频滤波抽取、符号同步和载波同步等模块的详细设计与实现。解调器结构简单,具有高度的稳定性、灵活性和可扩展空间,可以应用于通信、侦察接收机中。