ANSYS在VLSI互连模拟中的应用

介绍了ＡＮＳＹＳ程序在ＶＬＳＩ互连几何最佳化设计中的初步应用,应用表明：ＡＮＳＹＳ的模拟精度高,图形显示功能强,应用ＡＮＳＹＳ自动寻优功能使延迟最佳化几何参数的寻找较为迅速和直观。     

VLSI芯片制备中的多层互连新技术

在简要介绍多层互连材料的基础上,论述了若干种IC芯片制备中的多层互连技术,包括"Cu线 低k双大马士革"多层互连结构、平坦化技术、CMP工艺、"Cu 双大马士革 低k"技术、插塞和金属通孔填充工艺等,并提出了一些多层互连工艺中的关键技术措施.     

逆向统计模拟及在VLSI统计分析中的应用

本文在理论上提出了逆向统计模拟思想,并用以开发了NMOS数字集成电路统计模拟通用软件——STANMOS。应用该软件可定量得到工艺涨落及工艺干扰对电路性能的影响,分析电路性能的工艺灵敏度及成品率,确定主要影响电路性能一致性的工艺步骤。     

ULSI/VLSI中铝互连线热应力的数值模拟

对有钝化层与无钝化层的铝互连线的热应力进行了数值模拟,并建立起互连线的二维有限元模型.对无钝化的铝互连线,只考虑弹性行为,其应力随线宽及衬底刚度的增加而增加.对于钝化的铝互连线,对其弹性行为和弹性/理想塑性行为进行了模拟.结果发现,互连线线宽的减小,钝化层硬度的增加,都会使应力增加.与纯弹性线条相比,弹性/理想塑性互连线条中的应力有所减小,且分布更均匀.     

基于FDTD模拟综合VLSI互连线的时域特征模型

本文提出了大规模集成电路（ＶＬＳＩ）中互连线的特征模型，利用进域有限差分法（ＦＤＴＤ）模拟的响应电压和电流波形以及离散逆卷积技术，该特征模型直接在时域被数值综合。利用该模型，任何激励和负载条件下互连线的瞬态响应波形可以通过离散卷积运算迅速获得。     

VLSI互连线的全局优化算法

介绍了通过同时插入缓冲嚣和优化线宽达到互连线时延最小化的方法。为了同时插入缓冲器、优化缓冲嚣尺寸和优化线宽，可以扩展MASM(改进激活集合法)算法。计算结果表明，该算法非常有效。     

VLSI在通信系统中的应用

导致电气通信系统变革的主要原因是由于半导体大规模集成电路的引入。考虑到这种大规模集成电路对电气通信系统的发展有着积极的促进作用,武藏野电气通信研究所从1975年开始就把超大规模集成电路作为重点研究项目进行工作。本文将叙述电气通信系统与LSI之间的关系,特别是在电电公司通讯系统中大规模集成电路所占的地位。大规模集成电路在电电公司通讯系统方面的应用正在飞速进展,仅以LSI存储器为例,整个公司的使用量在最近4年内约增加了20倍(以位换算),约占日本国内使用量的2％。今后,电电公司打算利用数字化技术建立起一个为提供数据、传真等非电话对话服务业务所必要的通信网络,象这样一种数字技术的普及,将进一步提高大规模集成电路在通信系统中的作用。     

VLSI金属互连线电迁移噪声检测敏感性的逾渗模拟

在电迁移物理机制的基础上结合逾渗理论,建立了一种金属互连线电迁移的逾渗模型。基于该模型,采用蒙特卡罗方法模拟了超大规模集成电路（VLSI）金属互连线电迁移过程中电阻和低频噪声参数的变化规律。结果表明,与传统的电阻测量方法相比,低频噪声表征方法对电迁移损伤更敏感,检测的效率更高。该研究结果为低频噪声表征VLSI金属互连线电迁移损伤的检测方法提供了理论依据。     

VLSI互连寄生电容准三维多极加速提取

随着VLSI向深亚微米发展,需要快速而精确地计算互连寄生电容以保证高性能电路设计的正确性.本文介绍一个单介质准三维电容提取软件.在位势理论建立的间接边界积分方程中,它在导体表面采用线电荷近似面电荷的思想简化3-D结构,并采用多极加速法进一步降低计算复杂度.由于既保留了三维形体的空间架构,又使大量电荷积分降为一维,取得了精度与速度的良好平衡.数值计算结果表明,其计算复杂性为O(n),n为边界元数.     

大规模集成电路互连线的串扰估计

建立了一个基于电阻和电容的串扰分析模型,给出了干扰信号为线性倾斜信号时串扰的时域响应公式,得出了串扰峰值的估计公式,明确了干扰信号上升沿、互连线的电阻和耦合电容等对串扰的影响,并且利用Hyperlynx软件包进行仿真,仿真结果证明了理论分析的正确性.     

VLSI电路中互连线的延迟及串扰的数值模拟

用数值计算方法详细地模拟了VLSI电路中金属互连线的延迟及串扰.模拟结果表明:互连线宽W同互连线节距P之比W/P=0.5~0.6是获得最小时间延迟并满足串扰限制的最佳尺寸,模拟还给出了用铜代替铝金属线及用low-k电介质(ε_low-k=0.5ε_SiO2)代替SiO₂后,延迟及串扰的改善程度.     

Interconnect characterization of X architecture diagonal lines for VLSI design

This paper addresses the manufacturability, yield, and reliability aspects of X Architecture interconnects (diagonal lines) in a very large scale integrated (VLSI) design that enables integrated circuit (IC) chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130- and 90-nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line, and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance, and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan versus X Architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X Architecture designs.     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

VLSI互连线系统中的低介电常数材料与工艺研究

阐述了超大规模集成电路 ( VLSI)特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。具体总结了为提高 VLSI的速度而采用的低介电常数材料及其制备工艺 ,对在连线间形成空气间隙来降低线间电容的方法也进行了介绍。最后 ,展望了低介电常数材料在 VL SI互连线系统中的应用前景。     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect

Bundles of single-walled carbon nanotubes (SWCNTs) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current-carrying capabilities. Given the manufacturing challenges associated with future nanotube-based interconnect solutions, determining the impact of process variations on this new technology relative to standard copper interconnect is vital for predicting the reliability of nanotube-based interconnect. In this paper, we investigate the impact of process variations on future interconnect solutions based on carbon nanotube bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall three-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by up to 63% in 22-nm process technology     

VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance

This paper presents the architectural design of a multicomputer interconnection network based on the use of optical technology. The performance of the system is evaluated on a set of signal processing applications. The interconnect uses Vertical Cavity Surface Emitting Lasers (VCSELs) and flexible fiber image guides to implement a physical ring topology that is logically configured as a multiring. Processors in the multicomputer are nodes on the ring and extremely high communication bandwidth is possible. Using the Laser Channel Allocation (LCA) algorithm and the Deficit Round Robin (DRR) media access protocol, the bandwidth available in the optical interconnect can be reconfigured to make efficient use of the interconnect resources. A discrete-event simulation model of the interconnect is used to examine performance issues such as throughput, latency, fairness, and the impact of reconfigurability.Roger D. Chamberlain completed the degrees BSCS and BSEE in 1983, MSCS in 1985, and DSc (computer science) in 1989 all from Washington University in St. Louis, Missouri. He is currently an Associate Professor of Computer Science and Engineering at Washington University, where he is Director of the Computer Engineering Program. Dr. Chamberlain teaches and conducts research in the areas of computer architecture, parallel computing, embedded systems, and digital design.Mark A. Franklin received his BA, BSEE and MSEE from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently a Professor in the Department of Computer Science and Engineering at Washington University in St. Louis, Missouri, and holds the Hugo F. and Ina Champ Urbauer Chair in Engineering. He founded and is former Director of the Computer and Communications Research Center.Dr. Franklin is a Fellow of the IEEE and a member of the ACM. He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chair of the ACM SIGARCH (Special Interest Group on Computer Architecture). His research areas include computer and systems architecture, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation.Praveen Krishnamurthy received the Bachelor of Engineering degree from University of Madras (India) in 2000 and the MS degree in Computer Engineering from Washington University in St. Louis, Missouri, in 2002. He is currently a doctoral student at Washington University in St. Louis.Abhijit Mahajan received his B.E (Electronics) degree from University of Mumbai in 1998. He received is MSEE from Washington University in 2000. He is presently working with Broadcom Corporation in India. His main area of work is signal integrity and systems engineering.