MOSFET-Iike CNFET based logic gate library for low-power application： a comparative study

The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

A high-speed, low-power divide-by-4 frequency divider implementedwith AlInAs/GaInAs HBT's

The authors describe the first frequency divider demonstrated using AlInAs/GaInAs heterojunction bipolar transistors (HBTs). The divider (a static 1/4 divider circuit) operates up to a maximum frequency of 17.1 GHz, corresponding to a gate delay of 29 ps for a bilevel current-mode logic (CML) gate with a fan-out of 2, and a total power consumption of 67 mW (about 4.5 mW per equivalent NOR gate). These results demonstrate the potential of AlInAs/GaInAs HBTs for implementing low-power, high-speed integrated circuits     

p-capped GaN-AlGaN-GaN high-electron mobility transistors (HEMTs)

A novel p-capped GaN-AlGaN-GaN high-electron mobility transistor has been developed to minimize radio-frequency-to-dc (RF-DC) dispersion before passivation. The novel device uses a p-GaN cap layer to screen the channel from surface potential fluctuations. A low-power reactive ion etching gate recess combined with angle evaporation of the gate metal has been used to prevent gate extension and maintain breakdown voltage. Devices with gate lengths of 0.7 /spl mu/m have been produced on sapphire. Current-gain cutoff frequencies (f/sub /spl tau//) of 20 GHz and maximum frequencies of oscillation (f/sub max/) of 38 GHz have been achieved. Unpassivated devices demonstrated a saturated output power of 3.0 W/mm and peak power-added efficiency of 40% at 4.2 GHz (V/sub DS/ = +20 V).     

Design and Implementation of a Novel HomePlug-Based Solution for Low Cost and High Performance Smart Home Networking

As the smart home is the end-point power consumer, it is the major part to be controlled in a smart micro grid. There are so many challenges for implementing a smart home system in which the most important ones are the cost and simplicity of the implementation method. It is clear that the major share of the total cost is referred to the internal controlling system network; although there are too many methods proposed but still there is not any satisfying method at the consumers’ point of view. In this paper, a novel solution for this demand is proposed, which not only minimizes the implementation cost, but also provides a high level of reliability and simplicity of operation; feasibility, extendibility, and flexibility are other leading properties of the design.     

A Full Coverage Test Method for Configurable Logic Blocks in FPGA

FPGA＇s conflgurability makes it difficult for FPGA＇s manufacturers to fully test it. In this paper, a full coverage test method for FPGA＇s Conflgurable logic blocks （CLBs） is proposed, through which all basic logics of FPGA＇s every CLB can be fully tested. Innovative test circuits are designed using FPGA＇s internal resources to build Iterative logic arrays （ILAs） for Look-up tables （LUTs）, distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is transplantable and independent of FPGA＇s array size, so it can be applied to the test of different FPGAs. Xilinx＇s Virtex FPGA is taken as an example to explain our method, where only 19 test configurations are needed to achieve 100% coverage for all CLBs. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator- Turbofault is used to simulate FPGA＇s test coverage.     

An SEU-Tolerant Approach for Space-Borne Viterbi Decoders

In the space environment, Viterbi decoder implemented on SRAM-based FPGA is sensitive to Single event upsets （SEUs）, which may lead to functional failure of the decoder. Conventional SEU mitigation techniques like modular redundancy could not exploit the characters of Viterbi decoders, therefore could not provide optimized SEU tolerance when the device resource utilization cost is a constraint. Leveraging the properties of the decoding algorithm, three effective mitigation techniques are adopted, including structure optimization, Error detection and correction （EDAC） for Block RAM （BRAM） protection, and Partial triple-modular redundancy （PTMR）, which are applied to the modules of the decoder in accordance with their characteristics. Analysis of effectiveness shows that compared with unmitigated design, the SEU induced failure rate in the proposed SEU tolerant decoder can be reduced to 1/4 at the cost of 61.1% extra resource utilization. Error detec- tion and correction （EDAC）.     

Multigigahertz CMOS dual-modulus prescaler IC

A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L_eff=0.5 μm; V_dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L_eff=0.4 μm; V _dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

An Advanced Effective Capacitance Model for Calculating Gate Delay Considering Input Waveform Effect

In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance Ceff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.     

Quantum-Inspired Evolutionary Algorithm for Continuous Space Optimization

A quantum-inspired evolutionary algorithm based on the probability amplitudes of Quantum bits （qubits） is proposed. The chromosome is comprised of qubits whose probability amplitudes comprise gene chain. The qubits on chromosome are evolved by quantum rotation gates, and are mutated by quantum non-gates. For the rotation direction of quantum rotation gate, a convenient method is proposed. The formula of the magnitude of rotation angle is constructed based on the gradient of fitness function. In this method, the probability amplitudes of each qubit are regarded as two paratactic genes, each chromosome contains two gene chains, and each of gene chains represents an optimization solutiong which can accelerate convergence process for the same number of chromosomes. By two optimization examples of function extremum and of neural network weights, the experimental results show that the approach is superior to common quantum evolutionary algorithm and simple genetic algorithm in both search capability and optimization efficiency.     

A GaAs low-power normally-on 4-bit ripple carry adder

The realization and performance of a low-power buffered FET logic (1p-BFL) 4 bit ripple carry adder is reported. Performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included (27 mW without). This corresponds to an average propagation delay of 380 ps/gate (FI/FO=/SUP 5///SUB 3/), an average power consumption of 1.56 mW/gate, and a power-delay product of 0.6 pJ. Best speed performance biasing conditions yield a 1.25 ns critical path average propagation delay at a total power dissipation of 180 mW (180 mW excluding buffers), which corresponds to an average gate delay, power consumption and power-delay product of 250 ps, 6 mW, and 1.5 pJ, respectively. Standard cell layout techniques yield an average gate density of 200 gates/mm/SUP 2/, interconnection wiring included.     

Peak Power Minimizing Algorithm by Voltage Scheduling

For complicated electronic systems, to ensure high performance and reliability satisfaction, minimizing peak power consumption becomes one of the most important design goals. This paper addresses the problem of variable voltage scheduling on multlprocessor distributed systems, with the goal of shaping the power profile to minimizing peak power. A low peak power algorithm named LPPA is proposed to optimize power distribution via scaling voltage of the tasks on critical regions, based on the comprehensive analysis of how power consumption varies with latency. Compared with previous low peak power techniques, which simply scale voltage of tasks according to their timing critical degree, LPPA additionally take the power profile into count to further decrease the peak power. Experimental results show that the proposed voltage scheduling technique significantly improves the power characteristics over the existing power profile unaware scheduling technique. Meanwhile, energy consumption reduction is also obtained.     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

Infrastructure-Mediated Sensing Based Home Appliances Monitoring System Using the EMI Characteristics

An automatic monitoring system for home appliances using infrastructure-mediated sensing technology is presented. A practical solution for identifying the working states of electronic devices and determining the consumption of each device in a household is proposed. Initially, the components of Electromagnetic interference （EMI） noises in a residential power line are analyzed, and then the basic theory of Switched mode power supplies （SMPS） is discussed. Finally, a set of practical approaches has been proposed to detect and classify the electrical events, including a time-frequency transformation algorithm, power spectrum vector chasing, Gaussian function fitting and supervised pattern recognition, etc. The monitoring system has deployed into real houses and it successfully classifies SNIPS devices with accuracy from 92.6% to 99.2% for individual devices and 88.0% to 95.0% for multiple devices.     

High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

High-Speed and Low-Power GaAs Phase Frequency Comparator

A high-speed and low-power consumption phase frequency comparator (PFC) for a phase lock stable oscillator was designed and fabricated with a GaAs MESFET BFL circuit for the first time. The threshold voltage, gate width, and gate length of GaAs MESFET's in the PFC were determined by circuit simulations for a high-speed and low-power operation. The fabrication process used buried p-layer SAINT-FET's with 0.5-µm gate length. The fabricated PFC performed stable phase and frequency comparison up to 600 MHz at only 60 mW. Using dislocation-free wafers, the fabrication yield in the laboratory was more than 90 percent.     

Optimal operation of coreless PCB transformer-isolated gate drivecircuits with wide switching frequency range

Gate drive circuits for power MOSFETs and insulated gate bipolar transistors (IGBTs) often require electrical isolation. Coreless printed circuit board (PCB) transformers have been shown to have desirable characteristics from a few hundreds of hertz to a few megahertz and can be used for both power and signal transfer at low-power level. At low operating frequency, the magnetizing inductance has such low impedance that the driving power requirement could become excessive. This paper describes the use of a coreless PCB transformer for isolated gate drive circuits over a wide-frequency range. Based on a resonance concept, the optimal operating condition that minimizes the power consumption of the gate drive circuits is developed and verified with experiments. The coreless PCB transformer demonstrated here confirms a fundamental concept that the size and volume of a magnetic core could approach zero and become zero if the operating frequency is sufficiently high. Coreless PCB transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits and low-power converters. Their sizes can be much smaller than those of typical core-based pulse transformers. The electrical isolation of a PCB is much higher than that of an optocoupler     

低功耗CMOS低噪声放大器的分析与设计

基于TSMC 0.18μm CMOS工艺,设计了一种低功耗约束下的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源间并联一个电容,以优化噪声;并引入一个电感,与级间寄生电容谐振,以提高增益;通过减小晶体管的尺寸,实现了低功耗。模拟结果表明,在2.45 GHz工作频率下,增益大于14 dB,噪声系数小于1 dB,直流功耗小于2 mW。     

30-ps 7.5-GHz GaAs MESFET macrocell array

An ECL-compatible GaAs 250-gate macrocell array has been successfully designed and fabricated using a three-level series gate low-power source-coupled FET logic (LSCFL) and a newly developed 0.4- mu m-gate self-aligned MESFET process. The unloaded propagation delay time was 30 ps/gate at a 2.4-mW/gate power dissipation. The loaded delay time with fan-out=3 and a 2-mm line length was as fast as 74 ps. The flip-flop toggle frequency was 7.5 GHz. A 2*2 asynchronous transfer mode (ATM) switch circuit was constructed on the macrocell array, and a maximum operation frequency of 2 GHz was achieved.<>