低功率16位、175ksps、多通道ADC

凌特公司(Linear Technology)推出16位、8通道、175ksps、3V供电的模数转换器IXC1867L。该器件在全速工作时仅消耗2．7mW(MAX)功率，约为同类器件功耗的一半。并且当速度下降时，     

凌力尔特公司推出3款低功率16位、20MSPS模数转换器

2O12年10月22日,凌力尔特公司推出3款低功率16位、20MsPs模数转换器（ADC）LTC2269、LTC2270和LTC2271,从而为准确度非常高的DC测量提供最低输入参考噪声和严格的积分非线性误差（INL）。     

低功率、高速度的双通道ADC

凌特公司(Linear Technology)推出高速ADC系列LTC2220系列，包括从10Msps至170Msps范围的12位和10位分辨率ADC，以及高达80Msps的14位转换器。新推出的ADC系列是凌特公司以前推出的LTC1750系列5VADC的补充，这些低功率ADC适合诸如WCDMA蜂窝基站收发机、数字预失真功率放大器线性化和电缆调制解调器终端系统等应用。12位     

针对4G无线基站收发器的低功耗低失真混频器

IDTFll62是一款低功耗、低失真双路2300～2700MHz射频到中频混频器,拥有超线性（＋43dBm）三阶交调截取点（IP30）,可达到优异的互调抑制,是4G无线基站收发器中多载波、多模式蜂窝系统的理想选择。多达0．4dB的改进接收器SNR有利于无线通信运营商扩大覆盖面积和提高用户手机外围的可用数据率。     

低功率行动电话系统市场看好

台湾即将开放的低功率行动电话系统业务，因被认为是填补大哥大用户以外的一般消费用户需求的都会型产品，市场空间甚被看好，但因CT-2执照前已发放，如何升级换照经营，成为业关心的话题。     

低功率无线数据传输系统的研究与设计

分析了无线数据传输系统中影响其性能因素,提出了一种基于单片机控制,以的射频收发芯片nRF401为核心实现低功率无线数据传输的解决方案,研究分析了在低功率发射条件下采用高增益天线实现长距离无线数据传输的基本思路,给出了系统软、硬件设计方案。在某环境监测与报警系统中测试了系统性能,结果表明,该系统达到了预期的设计目标,并提出该系统的扩展应用思路。     

最低功率、16位、80Ms／sADC降低数据转换系统的噪声

凌力尔特公司（Linear Technology Corporation）推出低功率、16位、无漏码、80Ms／s模数转换器（ADC）LTC2259—16．其功耗仅为89mW,尚不及同类竞争16住解决方案的一半。LTC2259—16为现有的14位低功率LTC2259—14ADC系列提供了一种引脚兼容的升级,是具双倍数据速率（DDR）CMOS／LVDS输出的单通道16位ADC中功耗最低的一款。     

飞思卡尔推出低功率、高性能45nm PowerQUICC处理器

飞思卡尔采用45nm制造技术推出了高性能、低功率的MPC8569E PowerQUICC Ⅲ通信处理器。这款通信处理器是基于45nm绝缘硅片（SOI）技术的高性能、低功率器件,是先进的无线和有线通信设备应用的理想之选。它支持各种无线协议,同时可在小于10W功率范围内提供高达1．3GHz的性能。     

Proposed low power, high speed adder-based 65-nm Square root circuit

This paper focuses on the design of a 1-bit full adder circuit using Shannon’s theorem and adder-based non-Restoring and Restoring Square Rooter circuits. The proposed adder and Square Rooter schematics were developed using DSCH2 CAD tool, and their layouts were generated with Microwind 3 VLSI CAD tool. The Square Rooter circuits were analysed using standard CMOS 65-nm features with a corresponding voltage of 0.7 V. BSIM 4 was used to analyse the parameters. The proposed adder-based Square Rooter simulated results of the proposed adder with those of CPL, Static Energy Recovery Full (SERF), and CMOS adder cell-based Square Rooter circuits; the proposed adder-based Square Rooter circuit gives better results than the other adder-based Square Rooter circuits. We then compared the results with published results and observed that the proposed adder cell-based Square Rooter circuit dissipates lower power, responds faster, and has a higher EPI and higher throughput.     

1.5 V high speed low power CMOS current sense amplifier

A 1.5 V high speed low power current sense amplifier for CMOS SRAMs is described. The design is based on the current mode approach and it can be fabricated using a standard CMOS process. The sensing speed is independent of the bit and data line capacitances and no equalisation is needed during the read access. HSPICE simulations have shown that the proposed circuit outperforms the recently reported circuits in terms of speed and average power dissipation     

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements.<>     

SOI-DRAM circuit technologies for low power high speed multigigascale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty     

Bandwidth optimization of a low power,high speed CMOS current op amp

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2µm CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128M H z at a supply voltage of 3V and a supply current of 25µA. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.     

Low power low noise high speed tunable CMOS radiation detection system

This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascode charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-µm CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150 ns the power consumption of the entire channel is less than 5 mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5 pF. The output pulse has a peak amplitude of 200 mV for a charge of 10 fC from the detector and achieves a linearity better than 1% up to an input charge range of 12 fC.     

The MAJIC-FET: A high speed power switch with low on-resistance

For high power switching applications, it is desirable to have a semiconductor device that exhibits a low on resistance during current conduction in order to minimize the steady state conduction losses, and high speed turn-off to minimize the switching losses. The ideal device must operation at high current densities during forward conduction, minimizing the chip size required for any given current handling capability and lowering costs. This article describes a new device structure which realizes these features. In this device the injection of minority carriers from the gate junction controls its admittance.