用EBIC法观察InSb半导体器件中的p-n结

能够直观地"看到"半导体材料中制作的p-n结,对于半导体器件的设计和制造工艺很有意义,知道p-n结的厚度及其在样品中的位置,有利于设计器件的结构、保护膜的厚度、电极的尺寸等,也可以优化离子注入、表面处理、电路互联等工艺参数。本文用EBIC(电子束诱生电流)法观察了InSb半导体器件中的p-n结。同时观察到了器件中的肖特基结,其中肖特基结显示出明显的温度特性:温度降低,肖特基结响应区域扩大,温度降至80K,Cr-InSb肖特基结响应区域可扩展至47mm。用离子注入法在InSb材料中制成的p-n结其空间电荷区并不呈对称的空间分布,靠n区一侧的空间电荷区较薄,电荷密度较大,靠p区一侧的空间电荷区较厚,电荷密度相对较小。作为一种常用的观察分析工具,EBIC法在观察分析半导体器件结构方面有透视和显微等优点。     

聚酰亚胺对台面功率晶体管的钝化作用

自从半导体器件问世以来,半导体表面的钝化和保护一直是人们极为关注的问题.表面钝化技术已成为半导体工艺领域里的支柱.对于台面功率器件,如何保护好CB结暴露在外面的台面部分,是个尤为突出的问题,已耗去了人们巨大的精力.目前已发展有SiO_2钝化,非晶硅钝化、、多晶硅钝化、氮化硅钝化、磷硅玻璃钝化、玻璃钝化和聚酰亚胺钝化等多种方法.其中聚酰亚胺钝化,无需复杂的设备,成膜容易,工艺简单,而且这种钝化膜具有优良的热稳定性、化学稳定性、耐水性、电绝缘性、热膨胀系数小,与铝膜粘附力强、耐辐射.为此我们尝试用聚酰亚胺作为功率台面管的涂料,以期既可作为内涂料,又可弥补液相钝化膜太薄、结构疏松之不足,从而起到二次钝化的作用.     

多晶硅薄膜晶体管中的晶粒间界电荷分享效应

通过对晶粒间界两侧耗尽区建立准二维模型,研究晶粒间界电荷分享效应对多晶硅薄膜晶体管阈值电压的影响.研究表明,考虑了晶粒间界电荷分享效应的阈值电压将变小,其中晶粒尺寸对阈值电压的影响最大.在此基础上,建立了多晶硅薄膜晶体管的阈值电压解析模型.     

多晶硅薄膜晶体管的表面氮钝化技术

采用N2O和NH3等离子钝化技术对多晶硅薄膜表面和栅氧表面进行了钝化处理。实验结果表明,该技术能有效降低多晶硅薄膜的界面态密度,提高多晶硅薄膜晶体管性能,二次离子质谱分析表明在p-Si/SiO界面有氮原子富积,说明生成了强的Si-N键。     

聚酰亚胺薄膜表面微纳米尺度下电荷特性的研究

利用静电力显微镜(electrostatic force microscope,EFM)在微纳米尺度下对聚酰亚胺薄膜表面的电荷起因及特性进行研究.采用Dimension 3100型扫描探针显微镜的导电探针摩擦聚酰亚胺薄膜表面,在薄膜微纳米区域内产生电荷分布.通过静电力显微镜对微纳米区域产生的电荷进行表征,得出探针摩擦速度、探针电压对表面电荷的极性、密度、区域分布有很大的影响.同时也为微纳米尺度下探索聚合物绝缘材料表面电荷生成规律和机理提供了一个新的研究方法和途径.     

钝化前表面预处理对AlGaN/GaN HEMTs性能的影响

提出一种新的钝化技术--采用盐酸和氢氟酸混合预处理溶液(HF:HCI:H2O=1:4:20)对AIGaN/GaNHEMTs进行表面预处理后冉淀积Si3N4钝化,研究了新型钝化技术对AlGaN/GaN HEMTs性能的影响并分析其机理.与用常规方法钝化的器件相比,经过表面顶处理再钝化,成功地抑制了 AIGaN/GaN HEMTs肖特基特性的恶化,有效地增强抑制电流崩塌效应的能力,将GaN基HEMTs的输出功率密度提高到5.2W/mm,并展现良好的电学可靠性.通过X射线光电子谱(XPS)检测预处理前后的AIGaN表面,观察到经过预处理后的AIGaN表面氧元素的含量大幅度下降.表面氧元素的含量下降,能有效地降低表面态密度和表面电荷陷阱密度,被认为是提高AIGaN/GaN HEMTs性能的主要原因.     

钝化前表面预处理对AlGaN/GaN HEMTs性能的影响

提出一种新的钝化技术--采用盐酸和氢氟酸混合预处理溶液(HF:HCI:H2O=1:4:20)对AIGaN/GaNHEMTs进行表面预处理后冉淀积Si3N4钝化,研究了新型钝化技术对AlGaN/GaN HEMTs性能的影响并分析其机理.与用常规方法钝化的器件相比,经过表面顶处理再钝化,成功地抑制了 AIGaN/GaN HEMTs肖特基特性的恶化,有效地增强抑制电流崩塌效应的能力,将GaN基HEMTs的输出功率密度提高到5.2W/mm,并展现良好的电学可靠性.通过X射线光电子谱(XPS)检测预处理前后的AIGaN表面,观察到经过预处理后的AIGaN表面氧元素的含量大幅度下降.表面氧元素的含量下降,能有效地降低表面态密度和表面电荷陷阱密度,被认为是提高AIGaN/GaN HEMTs性能的主要原因.     

多晶硅薄膜晶体管泄漏区带间隧穿电流的建模

讨论了带间隧穿(BBT)效应在多晶硅薄膜晶体管所有的泄漏机制中占主导地位的条件因素,说明了在高场或低温情况下,泄漏电流主要来自带间隧穿.考虑了BBT的两个产生区域--栅漏交叠处和靠近漏端的PN结耗尽区,分析了陷阱态密度以及掺杂浓度对BBT电流的影响,最后提出了一个适用于多晶硅薄膜晶体管泄漏区的带间隧穿电流模型.     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

Space-charge layer capacitance and offset voltage of an exponential-constant p-n junction

It is important to study an exponential-constant p-n junction because it gives a realistic approximation for many diffused p-n junction profiles. To calculate the space-charge layer capacitance for this junction we use an abrupt space-charge edge approximation with a correction which includes the effect of the mobile carriers at the edges of the space-charge region. In this approach the offset voltage v_off is used in place of the built-in potential as obtained from the depletion approximation. An analytical model for the space-charge region capacitance for an exponential-constant junction is developed. This model holds well for zero bias, for small forward voltages, and for reverse voltages. It shows good agreement when compared with the Chawla-Gummel model. It is simple and gives a direct relationship between the depletion capacitance and the applied voltage.     

Characterization of space-charge properties of a linearly graded p-n junction by an approximate "Regional" analysis method

A new approximate analysis of the linearly graded p-n junction is developed which gives solutions for the space-charged density and mobile carrier densities as distributions within a finite space-charge width. The results obtained are in good agreement with the true unbounded solution of Poisson's equation and represent a considerable improvement in space-charge modeling over previous approaches to approximate "regional" analysis. The solution process is implemented numerically as a computer algorithm in terms of either the total junction space charge or the applied voltage as a parameter; it is appropriate for application in the analysis of devices by the regional method where modeling of space-charge and mobile carrier distributions is required. Results are presented for the space-charge density distributions of linearly graded junctions; also for the space-charge capacitance and total junction capacitance including the high forward bias region.     

Improving reliability of beveled power semiconductor devices passivated by SIPOS

Semi-insulating polycrystalline silicon films were prepared by direct current glow discharge on bevelled power semiconductor devices. Devices passivated by polyimide were also fabricated for comparison studies. The reverse current–voltage characteristic was studied at room temperature and high junction temperature. The differences arose from the remnant unbalance charges in the passivants as well as the varying dielectric strengths. Passivation materials applied to the beveled devices played a key role in achieving the targeted voltage. Results obtained indicated that the performance of power semiconductor devices passivated by SIPOS were superior to those passivated by polyimide, and SIPOS based process was effective and expected to enhance the reliability and yield.     

Forward-voltage capacitance and thickness of p-n junction space-charge regions

A comprehensive analytical model for the quasi-static capacitance of the space-charge region of p-n junction devices is presented. It describes the capacitance for all voltages, including voltages large enough to cause the junction barrier to vanish. The model applies for exponential-constant doping profiles, the limiting cases of which are the step and the linear-graded profiles. In addition to the analytical model, an iterative technique is developed to yield numerically the thickness of the space-charge region as a function of voltage. The capacitance model shows good agreement when compared with measured dependencies, With an empirical model for circuit simulation, and with models based on device simulation. The model extends previous replacements of the depletion capacitance, provides a tool for circuit simulation, and is intended to provide understanding of the physics related to storage of mobile holes and electrons in the junction space-charge region.     

Experimental verification of inhomogeneous field distribution in negatively bevelled high-voltage p-n junctions by means of photomultiplication

Laser-beam-excited photocurrent measurements of the space-charge layer width close to the surface of a negatively bevelled diffused p-n junction revealed the existence of a well defined region of carrier multiplication at high applied voltages. The region is located within the space-charge layer on the highly doped side of the junction and close to the surface. The laser-light wavelength was 6328 ? and the beam diameter was about 5 ?m. The experimental results are consistent with the theoretically predicted existence of a field maximum in this region of negatively bevelled p-n junctions.     

High-frequency barrier capacitance of metal-semiconductor contacts and abrupt p-n junctions

Semiconductors - High-frequency capacitance of a Schottky barrier and an abrupt p-n junction are calculated taking into account the free charge carrier concentration in the space-charge region of a...     

Effects of ionizing radiation on oxidized silicon surfaces and planar devices

This paper examines in detail the effects of high and low energy electron, X-ray, and ultraviolet radiation on oxidized silicon surfaces and planar devices. Two permanent effects of ionizing radiation on oxidized silicon surfaces are distinguished: 1) The buildup of a positive space charge within the oxide, and 2) The creation of fast surface states at the oxide-silicon interface resulting in increased surface recombination velocity. The dependence of these effects on dose and dose rate, on bias applied during irradiation, and on structural parameters is discussed and a theory is presented which accounts for the observed features of the space-charge buildup. This theory involves trapping of holes which are generated within the oxide by the radiation. It is shown that all details of the experimental observations can be accounted for by assuming a high density of hole traps near the oxide-silicon interface which decays rapidly with distance into the oxide. Radiation-induced changes in the characteristics of MOS and junction field-effect transistors, p-n junction diodes, and p-n-p and n-p-n transistors are reported and examined in terms of the above two effects. It is shown that the charge buildup causes shifts in the operating point of MOS transistors, catastrophic increases in the reverse current of p-n junctions, and variations in their breakdown voltage. The increase in fast surface-state density is responsible for the lowering of the transconductance of MOS transistors and, in combination with the space-charge buildup, for the degradation of the current gain in bipolar transistors. It is shown that junction field-effect transistors are relatively insensitive to both effects of ionizing radiation and therefore offer the most promise for use in ionizing radiation environments.     

Comparison of DMOS/IGBT-compatible high-voltage terminationstructures and passivation techniques

Single and multiple field plates are considered in conjunction with field-limiting rings and junction terminal extension (JTE) junction terminations with and without an additional SIPOS passivation. This comparison is done for shallow p-n junctions on n-type substrates doped to 1-2×10¹⁴ cm^-3 for 500- or 1000-V devices, respectively. The conclusions obtained from two-dimensional numerical simulations are checked experimentally. The best results have been obtained using a JTE structure with SIPOS passivation     

Analysis of field effect transistors with arbitrary charge distribution

Solutions of field effect equations in which carrier density and space-charge distributions are considered in general form show that the LF terminal characteristics are not strongly dependent on the shape of the distribution curves. General expressions for mutual transconductance, output conductance, junction capacitance and current amplification are derived as functions of the depletion layer thickness at the device boundaries. These expressions are not explicitly dependent on charge distribution. Relationships between the small-signal and dc terminal characteristics depend on the shape of the charge distribution curves but cannot be varied by more than a factor of two. The shape of the device is shown to have secondary importance.     

Depletion layer characteristics at the surface of beveled high-voltage P-N junctions

The design of high-voltage p-n-junction devices used today is usually based on beveling of the p-n junctions in order to reduce the tangential surface field far enough below the bulk field and to secure thus that breakdown occurs in the bulk of the device rather than at the surface. Using relaxation methods, solutions of Poisson's equation in two dimensions have been found which reveal that for commonly used bevelings of the forward-blocking junction in a thyristor structure, the electric field in the region below the surface is larger than in the bulk and at the surface. This field is strongly dependent on surface charges. It is shown that bevelings avoid the surface breakdown but the body breakdown obtained is not the true bulk breakdown as expected but rather occurs in the immediate neighborhood to the surface. The calculations make it possible to obtain the breakdown voltage for beveled structures. Measurements of the tangential surface field obtained by probing the junctions, light-spot measurements of the space-charge-region width on the surface and capacitance measurements of the surface charge as well as breakdown measurements are in good agreement with the calculations. This approach has led to the design of high-voltage thyristor structures that exhibit true bulk breakdown and, at the same time, loss of semiconducting material due to beveling is reduced.