A buck converter with adaptive on-time PFM control and adjustable output voltage

This letter proposes a new adaptive on-time pulse-frequency modulation (PFM) circuit that operates at a wide range of supply voltage levels and that can generate various output voltage levels compared to conventional circuits. The circuit’s peak inductor current is well-controlled; the magnitude of the output ripple voltage is constant, even when the supply and output voltage levels are significantly different. Since the ripple voltage is a noise component, constant ripple voltage is important for predictable noise of a power management system.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control

Integrated switching power supplies with multimode control are gaining popularity in state-of-the-art portable applications like cellular phones, personal digital assistants (PDAs), etc., because of their ability to adapt to various loading conditions and therefore achieve high efficiency over a wide load-current range, which is critical for extended battery life. Constant-frequency, pulsewidth modulated (PWM) switching converters, for instance, have poor light-load efficiencies because of higher switching losses while pulse-frequency modulation (PFM) control in discontinuous-conduction mode (DCM) is more efficient at light loads because the switching frequency and associated switching losses are scaled down with load current. This paper presents the design and integrated circuit prototype results of an 83% power efficient 0.5-V 50-mA CMOS PFM buck (step-down) dc-dc converter with a novel adaptive on-time scheme that generates a 27-mV output ripple voltage from a 1.4- to 4.2-V input supply (battery-compatible range). The output ripple voltage variation and steady-state accuracy of the proposed supply was 5 mV (22-27 mV) and 0.6% whereas its constant on-time counterpart was 45 mV (10-55 mV) and 3.6%, respectively. The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance     

Buck型变换器的线性化小信号补偿前馈控制

为减小由输入电源扰动引起的输出电压工频纹波,改善DC/DC变换器动态性能,根据平均变量建模思想,为电压型PWM控制的Buck型变换器建立连续导电工作模式（CCM）下统一的平均变量等效电路。分析等效电路并根据前馈控制的不变性原理提出Buck型变换器针对输入电压扰动的线性化小信号补偿前馈控制原理及实现方法,采用该方法的Buck型变换器可快速补偿输入电压扰动,加快变换器在输入电压扰动时的动态调节过程,显著减小输出电压中包括工频在内的低频纹波,改善变换器的动态性能。仿真研究结果验证了文中线性化小信号补偿前馈控制原理、方法及其分析的正确性。     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

A Single Phase Voltage Regulator Module (VRM) With Stepping Inductance for Fast Transient Response

A single-phase fast transient converter topology with stepping inductance is proposed. The stepping inductance method is implemented by replacing the conventional inductor in a buck converter by two inductors connecting in series. One has large inductance and the other has small inductance. The inductor with small inductance will take over the output inductor during transient load change and speed up dynamic response. In steady state, the large inductance takes over and keeps a substantially small ripple current and minimizes root mean square loss. It is a low cost method applicable to converters with an output inductor. A hardware prototype of a 1.5-V dc-dc buck converter put under a 100-A transient load change has been experimented upon to demonstrate the merit of this approach. It also serves as a voltage regulator module and powers up a modern PC computer system     

A novel high efficiency low ripple switched-capacitor DC/DC converter

This paper presents a new method to improve light load efficiency and minimize output ripple of switched-capacitor (SC) DC/DC converters. In order to improve light load efficiency, this paper proposes adaptive frequency modulation to scale down gate-drive losses as load current reduces. Adaptive duty cycle modulation is proposed to minimize output ripple as the converter works under different gain hopping mode. Furthermore, this work optimized switching frequency, the dead time of 2-phase non-overlapping clocks and switching transistor size for efficiency enhancement. A new compensation circuit is also proposed to make system stable. A transistor level implementation of the proposed SC converter in Chartered 0.35 μm CMOS process is provided. Measurement results shows: maximum ripple voltage is <8 mV and efficiency is up to 87%.     

自适应开启时间的Buck型DC-DC控制器设计实现

设计了一种基于自适应开启时间(adaptive on-time, AOT)控制的Buck型DC-DC控制器电路,利用输入电压前馈和输出电压反馈技术来获得开启时间,并提出了一种充电电流补偿和充电时间超前电路,校正了开启时间的线性度.AOT控制保证了转换器在无需内部振荡器的条件下,工作于固定频率脉冲宽度调制模式,并改善了输出电压的纹波特性.AOT控制使系统在负载阶跃时能够连续开启最小关断时间的开关周期或连续关断,从而快速调节电感电流,极大地提高了系统的瞬态响应速度.自动跳跃式脉冲频率调制模式,有效地改善了轻负载下的转换效率.芯片采用UMC 0.6μm BCD工艺投片验证,并出了详细的测试结果.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.     

A Buck-Derived Topology With Improved Step-Down Transient Performance

The slew rate of the inductor current is limited by the inductance value and the voltage across the inductor. In a buck converter, when the controller is saturated, the voltage across the inductor during a step-up load transient is $V_{rm in}-V_{rm out}$, while during a step-down load transient, it is $-V_{rm out}$. Thus, a buck converter with a large conversion ratio offers asymmetrical step-up and step-down transients. Since the rate of fall of the inductor current is much slower than the rate of rise of the inductor current, the step-down transient lasts longer than the step-up transient for the same change in the load current. The step-down slew rate can be increased by reducing the inductance, but it results in higher inductor current ripple, and hence, higher losses in the power converters. In this paper, we present a novel topology for improving the step-down load transients without reducing the inductance value. The scheme operates only during load transients and restores to the normal operating conditions during steady-state operation. It provides reduced voltage overshoots and faster settling times in output voltage during such transients. The proposed scheme is tested on a 1-V/12-A buck converter switching at 1 MHz, and the experimental results are presented.      

A 1500 mA,10 MHz on-time controlled buck converter with ripple compensation and efficiency optimization

正A 1500 mA,10 MHz self-adaptive on-time(SOT) controlled buck DC-DC converter is presented.Both a low-cost ripple compensation scheme(RCS) and a self-adaptive on-time generator(SAOTG) are proposed to solve the system stability and frequency variation problem.Meanwhile a self-adaptive power transistor sizing(SAPTS) technique is used to optimize the efficiency especially with a heavy load.The circuit is implemented in a 2P4M 0.35μm CMOS process.A small external inductor of 0.47μH and a capacitor of 4.7μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV.The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling(DVS) performance is a rise of 16μs/V and a fall of 20μs/V.With a SAPTS technique and PFM control,the efficiency is maintained at more than 81%for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.     

一款电流型控制的DC／DC降压转换器

本文提出一种新型电感电流检测电路,该检测电路不需要一个放大器作为电压镜像,从而使用的器件更少,功耗更低。该电感电流检测电路应用于DC／DC降压转换器,采用CSM 0．18μm CMOS工艺进行设计和仿真,仿真结果显示该电感电流检测电路的精度可达到96％,输出电压的纹波仅为1mV。     

Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC–DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC–DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC–DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC–DC converters operating at switching frequencies up to 10 MHz and above.     

一种新型交错并联同相降压升压DC/DC转换器

为了有效降低电流纹波和提高转换器效率,提出一种新型交错并联同相降压升压DC/DC转换器。提出的结构通过采用输入/输出（I/O）磁耦合交错并联和阻尼网络技术,降低了开关的电压应力、内部电压振荡和I/O电流纹波,并提升了转换器的效率。采用状态空间平均法,在连续导通模式下分析了提出转换器的稳态运行,从理论上证明了其优势。样机的功率设置为360W,输出电压为36 V,模拟结果以及实验结果显示,当输出电流为6A时,转换效率最高达到96%,最大输入电流纹波百分比仅为9.4%,相较于其他类似转换器,提出的转换器具有效率较高和I/O电流纹波较低的优势。     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.     

A TEG Efficiency Booster with Buck–Boost Conversion

A thermoelectric generator (TEG) efficiency booster with buck–boost conversion and power management is proposed as a TEG battery power conditioner suitable for a wide TEG output voltage range. An inverse-coupled inductor is employed in the buck–boost converter, which is used to achieve smooth current with low ripple on both the TEG and battery sides. Furthermore, benefiting from the magnetic flux counteraction of the two windings on the coupled inductor, the core size and power losses of the filter inductor are reduced, which can achieve both high efficiency and high power density. A power management strategy is proposed for this power conditioning system, which involves maximum power point tracking (MPPT), battery voltage control, and battery current control. A control method is employed to ensure smooth switching among different working modes. A modified MPPT control algorithm with improved dynamic and steady-state characteristics is presented and applied to the TEG battery power conditioning system to maximize energy harvesting. A 500-W prototype has been built, and experimental tests carried out on it. The power efficiency of the prototype at full load is higher than 96%, and peak efficiency of 99% is attained.     

Fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck converter

A fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck is proposed for enhancing the transient characteristics of switching DC–DC converters and fabricated with TSMC 0.35 μm DPQM CMOS processes. By adopting a hysteresis-current-controlled DC–DC buck converter, it is demonstrated that the hysteresis-current-controlled technique have improved dynamic response of load variations whether the load current is light or heavy. Fast-response structure achieves 5 μs response with load variation which betweens 10 and 110 mA. Also proposed single-inductor dual-output structure is a time-multiplexing circuit to decrease the influence of cross regulation than that of previous designs. With a 3.6 V input power supply, the DC–DC buck converter precisely provides an adjustable power output with a voltage range from 0.9 to 3 V.     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。     

Integrated on-chip 0.35 μm BiCMOS current-mode DC–DC buck converter

A current-mode DC–DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC–DC converter is fabricated with 0.35?µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3?MHz switching frequency with a supply voltage of 5?V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30?µH off-chip inductor and 100?µF off-chip capacitor.     

一种新型基于二次型Buck变换器的交错并联LED驱动电源

为了减小输出电流纹波,提出了一种基于二次型Buck变换器的交错并联LED驱动电源。主电路由一个二次型Buck变换器和一条新增支路构成,这条新增支路包括一个开关管、二极管、电感和电容,优化了原有的拓扑结构,实现了高功率因数和恒流输出。采用交错并联技术,有效减小了滤波电感和输出电流纹波,纹波大小仅为输出电流峰峰值的0.18%。最后通过实验样机详细验证了理论分析的正确性。