A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.     

Elliptic filtering in continuous-time sigma-delta modulator

An improved continuous-time sigma-delta (/spl Sigma//spl Delta/) architecture with elliptic signal transfer function is presented. It is demonstrated that the UTRA/FDD band 1 interferer filtering can be fully achieved within the sigma-delta loop.     

A sixth-order continuous-time bandpass sigma-delta modulator fordigital radio IF

This paper presents a sixth-order continuous-time bandpass sigma-delta modulator (SDM) for analog-to-digital conversion of intermediate-frequency signals. An important aspect in the design of this SDM is the stability analysis using the describing function method. The key to the analysis is the extension of the linear gain model for the sampled quantizer with a phase uncertainty. The single-loop, one-bit SDM is tuned at 10.7 MHz, is sampled at 40 MHz, and achieves 67-dB signal-to-(noise+distortion) ratio in 200 kHz and 80 dB in 9 kHz. The third order intermodulation is at -82 dBc for a -13-dBFS input level. The 0.5-μm CMOS chip occupies 0.9×0.4 mm² and consumes 60 mW at 3.3 V (digital) and 5.0 V (analog). The sample frequency is variable and can be set from 30 to 80 MHz     

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

A novel noise-shaping DAC for multi-bit sigma-delta modulator

This paper describes a new noise-shaping technique for reducing the noise of the internal digital-analog conversion (DAC) in multi-bit low-pass sigma-delta modulators. The proposed technique works with most existing dynamic element matching (DEM) algorithms to provide noise shaping to the DAC noise. The simulation shows that a 10-dB improvement in the signal-to-noise conversion ratio can be obtained with the proposed noise-shaping with DEM (NSDEM) technique. A dithered DAC employing NSDEM is realized in a 0.35-/spl mu/m CMOS process and the test result shows the first-order high-pass noise shaping to the DAC noise, and validates the proposed concept.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

A fourth-order bandpass sigma-delta modulator

The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio     

A first-order current-steering sigma-delta modulator

A new architecture is presented for a first-order sigma-delta (ΣΔ) modulator. The system achieves a high sampling frequency, can be used as a building block for higher-order modulators, and uses circuit techniques that are largely independent of a specific technology. The key features of this implementation are that it operates in a continuous-time (as opposed to switched) mode and does not need feedback amplifiers. To test the validity of the concept, the system was realized in 2-μm, n-well, double-metal, single-poly technology. It has a measured resolution of 9 b and a linearity of 13 b at a clock frequency of 20 MHz with an oversampling ratio of 128. It operates from a power supply of ±2.5 V with a power consumption of 3 mW. The circuit occupies an area of 0.92 mm²     

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2.     

A third-order sigma-delta modulator with extended dynamic range

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution analog-to-digital conversion in VLSI technology. Because high-order noise shaping greatly reduces the quantization noise in the signal band, the dynamic range of these modulators tends to be bounded by the thermal noise of the input stage and the maximum voltage swing in the signal path. This paper introduces a third-order cascaded sigma-delta modulator that uses a modified cascaded architecture and reduced gain in the first integrator to increase the dynamic range. An experimental modulator fabricated in a 1-μm CMOS technology attains a resolution of 17 b for a 25-kHz signal bandwidth while operating from a single 5-V supply. With an oversampling ratio of 128 and a clock frequency of 6.4 MHz, the modulator achieves a 104-dB dynamic range and a peak signal-to-noise+distortion ratio (SNDR) of 98 dB. As indicated by both measurements and simulations, the cascaded architecture also greatly reduces the discrete noise peaks that can be present in a single-stage architecture     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

A wideband cascaded sigma-delta modulator with improved nonlinearity effects

This work presents a wideband cascaded sigma-delta modulator (CLFSDM) that reduces the nonlinearity effects of components. This architecture offers a new noise-shaping function to achieve high resolution in wideband applications and reduce digital-analogue converter (DAC) mismatch from the multi-bit feedback. Moreover, the error cancellation schemes can be added in the digital circuit part to cancel the coarse quantization errors and thus effectively reduce the non-ideal effects such as DAC mismatch. The mismatches between the two stages, such as in the gain error and pole error, may seriously degrade performance. The blind on-line calibration technique is used to eliminate these imperfect analogue circuit errors in the digital circuit. Accordingly, this architecture can reduce the over sampling ratio (OSR), and the in-band noise can be significantly suppressed to achieve a high resolution in Matlab and Switcap2 simulations. Simulation results indicate this sigma-delta modulator is very efficient in wide bandwidth applications.     

A time-domain noise-coupling technique for continuous-time sigma-delta modulators

In this paper, a time-domain noise-coupling technique based on the pulse width modulation is proposed. The time-domain quantization error is digitally extracted and shaped by an asynchronous digital filter. This digitally filtered quantization error is applied to the quantizer input to increase the modulator’s noise-shaping order. By using this technique in continuous-time sigma-delta modulators, the modulator’s shaping property is significantly enhanced. Comparative analytical calculations and simulation results are presented to estimate the performance of modulators employing the proposed quantizer. System-level simulation results reveal a (L + 2)th order noise-shaping capability of the proposed modulator while it employs only L analog integrators. The effects of main circuit non-idealities in the modulator’s performance are analytically investigated and confirmed by the simulation results.     

A high resolution multibit sigma-delta modulator with individuallevel averaging

A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 μm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 kHz baseband. No tone is observed in the baseband as the amplitude of a 10 kHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply     

A third-order multistage sigma-delta modulator with reducedsensitivity to nonidealities

A multistage third-order sigma-delta modulator, which is unconditionally stable and has a low sensitivity to component mismatch and op-amp performance limitations, has been designed and fabricated in a 1.2-μm CMOS double-poly technology. The modulator, consisting of cascaded second- and first-order stages, is scaled to prevent performance degradation from integrator overload. In addition, the first-stage integrator output is used directly, instead of its quantization error, to facilitate ratioless input circuitry in the second stage. Experimental results indicate a signal-to-noise ratio of 93 and 90 dB at a signal-to-distortion ratio of 93 dB for sample rates of 24 and 80 kHz, respectively     

A wideband CMOS sigma-delta modulator with incremental dataweighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-μm CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm². Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance     

A current-mode power sigma-delta modulator for audio applications

Linear and switching techniques are currently adopted to implement current-mode power stages. Pulsewidth modulation (PWM) is usually employed with the switching technique for both industrial and audio applications. In this paper, the Sigma-Delta modulation is considered as an alternative to the PWM in devising a switching current-mode power stage suitable for audio amplification. The proposed modulator is analyzed and simulated. The whole system was realized on an experimental breadboard. The results carried out on the prototype are reported and discussed. The electrical characterization presents interesting features in terms of linearity, noise, and power efficiency.