A LIDAR sensor prototype with embedded 14-bit 52 ps resolution ILO-TDC array

High resolution light detection and ranging (LIDAR) systems enable rapid imaging and mapping for applications such as autonomous vehicles and robotics. This paper presents a high-resolution LIDAR sensor system-on-a-chip (SoC) prototype containing a 31 × 2 pixel channel array with the input time-of-flight resolved by a 32 × 1 time-to-digital converter (TDC) array. A low-power avalanche photodiode (APD) receiver front-end with output bit-line sharing allows an array implementation and achieves ? 22 dBm sensitivity. Injection-locked oscillators (ILOs) are utilized in a TDC design to both minimize clock distribution power and improve timing accuracy. An on-chip phase-looked loop calibrates for ILO global PVT variations and ensures reliability over a wide operating range. Fabricated in GP 65 nm CMOS, the 14-bit TDC consumes 788 μW/channel and achieves 52 ps resolution over an 830 ns full-scale range, 37.2 ps_rms single-shot precision, 11 ps_rms channel uniformity, and DNL/INL of 0.56/1.56 LSB, respectively. This electrical characterization projects that the SoC has the potential for 0.78 cm ranging precision over a 124 m maximum ranging distance. Sensor testing with a pulsed laser and an APD array hybrid-integrated with the CMOS SoC shows a measurement range of over 700 ns with a 3.2 ns maximum single-shot error.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

Freewheel charge-pump controlled single-inductor multiple-output step-up DC–DC converter

This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC–DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 μH inductor, 4.7 μF charge-pump capacitors and 33 μF output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies 1.3 × 1.3 mm². Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for V_O1, V_O2, V_O3 and V_O4, respectively.     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

An Implantable CMOS Front-End System for Nerve-Signal Sensors

An analog front-end dedicated to processing of cuff-recorded human nerve signals is presented in this paper. The system is comprised of a low-noise preamplifier and an A/D converter (ADC) for quantizing the recorded nerve signal. The instrumentation amplifier utilizes CMOS transistors biased in the weak/moderate inversion region at a relatively high current for low thermal noise performance and achieves low flicker noise performance through chopper stabilization. The resulting measured equivalent input referred thermal noise is 6.6 nV/√Hz at a chopping frequency of 20 kHz. A two-stage design is implemented which achieves a measured amplification of 72.5 dB over a signal bandwidth of 4 kHz. For the ADC, a third order ΣΔ-modulator employing a continuous-time (CT) loopfilter was implemented. Each of the integrators in the loop-filter are implemented as G _m ?C elements. For a sampling frequency of 1.4 MHz, the measured SNDR for the ADC is 62 dB, whereas the dynamic range (DR) is 67 dB over a 4 kHz bandwidth, equivalent to a resolution of 10 bits. The system draws a current of 196 μA from a 1.8 V supply thus consuming approximately 350 μW excluding buffers and bias circuitry.     

A 0.6 V and 0.395 pJ/bit nonius TDC for a passive RFID pressure sensor tag

This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 μs. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.     

A novel low power flip-flop design using footless scheme

A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single stage with no use of operational amplifiers. Chopper stabilization technique is utilized to reduce 1/f noise for minimizing the in-band integrated noise. Implemented and simulated in a 0.18 μm CMOS process, the 3rd-order LPF achieves a ??3 dB bandwidth of 20 MHz with a 280 μA total current from a 1.4 V supply voltage, defining a power-per-pole/bandwidth efficiency of 6.5 μW/MHz. The output noise density at low frequencies is largely reduced with chopper stabilization technique. The integrated output noise from 10 kHz to 2 MHz is minimized from 22.47 to 7.04 μV_rms, with a 10.1 dB improvement. The averaged output noise density over the filter bandwidth is 9.4 nV/√Hz, which is mostly contributed by thermal noise of transistors.     

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 μm CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 μW and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm².     

A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divider-less ADPLL

This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoM_P without requiring complicate calibration.     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.     

A multiple-output switched-capacitor DC–DC converter for individual brightness control of RGB LEDs with time-interleaved control and output current regulation

In this paper, an integrated multiple-output switched-capacitor (SC) converter with time-interleaved control and output current regulation is presented. The SC converter can reduce the number of passive components and die areas by using only one flying capacitor and by sharing active devices. The proposed converter has three outputs for individual brightness control of red–green–blue (RGB) LEDs. Each output directly regulates the current due to the V–I characteristics of LEDs, which are sensitive to PVT variations. In the proposed converter, the current-sensing technique is used to control the output current, instead of current-regulation elements (resistors or linear regulators). Additionally, in order to reduce the active area, three outputs share one current-sensing circuit. In order to improve the sensing accuracy, bias current compensation is applied to a current-sensing circuit. The proposed converter has been fabricated with a CMOS 0.13-μm 1P6M CMOS process. The input voltage range of the converter is 2.5–3.3 V, and the switching frequency is 200 kHz. The peak power efficiency reaches 71.8 % at V _IN =2.5 V, I _LED1 = 10 mA, I _LED2 = 18 mA, and I _LED3 = 20 mA. The current variations of individual outputs at different supply voltages are less than 0.89, 0.72, and 0.63 %, respectively.     

A 95 nA quiescent current hysteretic mode buck converter with sample and hold reference

A nano ampere (nA) hysteretic mode buck converter is presented in this paper. Nano ampere current sleep phase and fast response burst phase are implemented. The converter achieves nano-watt power consumption in sleep phase while ensures fast wake-up from sleep phase to burst phase. New developed ultra low power sample-hold voltage reference and 1 kHz oscillator draw currents of 20 and 10 nA respectively. The circuit was implemented in a 0.35 μm CMOS process. The measurement result shows that the converter’s quiescent current (Iq) in sleep phase is as low as 95 nA. Benefit from the ultra-low Iq, the circuit achieves conversion efficiency of 79.8% at 2 μA load, regulating output at 2.5 V with a 3.6 V supply. The peak efficiency is up to 94% at 50 mA load.     

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

We present a new noise shaping method and a dual-polarity calibration technique suited for successive approximation register type analog to digital converters (SAR–ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR–ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3 μW power with 1.8 V supply.     

CMOS integrated MPP tracker with analog power measurement at the PV converter input

An integrated converter controller with maximum power point (MPP) regulation in 0.35 μm CMOS for photovoltaic (PV) applications is reported. The implemented MPP tracker bases on a perturb and observe algorithm and acquires the information concerning the power flow via an analog processing circuit which is connected at the switched mode converter input respectively the output of the attached PV string of nine cells. There the solar cell current is measured via a very low-ohmic shunt resistor of 1 mΩ and analogously multiplied with the cell voltage. As output the fabricated test chip directly generates a 530 kHz PWM signal for the external switched mode converter. Measurements show that under similar conditions analog MPP tracking of the converter input power improves the robustness with respect to settling times of the power path compared to those topologies at which the power is measured at the converter output. Between 0.4 and 7.5 A photocurrent the chip achieves tracking efficiencies better than 99.5 % while the power consumption is only 750 μW and a very low chip area demand of 0.043 mm² for the MPP tracking core is achieved.     

Design and analysis of high speed capacitive pipeline DACs

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mV_pp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 < ?70 dB and HD2 < ?90 dB over 0.5–5 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. High linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz with Nyquist sampling. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.     

A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system

A combined successive approximation (SAR) capacitance-to-digital converter (CDC)/analog-to-digital converter (ADC) for biomedical multisensory system is presented in this paper. The two converters have same circuit blocks and can be exchanged by four switches. Capacitance or voltage from different sensing elements can be measured and converted to digital output directly. This single chip takes place of separated CDC and ADC so that the power consumption of the multisensory system is reduced. The asynchronous SAR circuit has low power and small area. A dynamic comparator with zero-static power is adopted. Switches are carefully designed to reduce the non-idealities of the converter. Several techniques, such as bootstrapped switches, bottom-plate sampling, dummy switches are used to improve the performance of the circuit. The CDC/ADC is fabricated in 0.18 μm CMOS process. Measurement results show that the ENOB of this 11 bits converter is 10.15 bits and its FOM is 45 fJ/conversion-step under 200 kHz sampling. The power consumption is 9.4 μW with 1.4 V power supply voltage and the core area is 0.1764 mm².     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at P_in = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.