a—Si：H TFT有源矩阵制造技术的研究

对ａ：Ｓｉ：Ｈ ＴＦＴ有源矩阵的一些关键制造工艺进行研究。研究了Ｔａ２Ｏ５／ａ－ＳｉＮｘ双绝缘层的制备技术，提出了一种新的双有源层结构ａ－Ｓｉ：Ｈ ＴＦＴ来降低背光源对器件特性的影响，研制的ａ－Ｓｉ：Ｈ ＴＦＴ有源矩阵实现了彩色视频信号的动态显示。     

自对准结构α—Si：H TFT特性的分析和研究

本文描述了用自对准工艺制备自对准结构的αＳｉ：Ｈ ＴＦＴ。从理论上分析了有源层α－Ｓｉ：Ｈ的厚度对α－Ｓｉ：Ｈ ＴＦＴ特性的影响，据此提出一种新型的双有源层结构的α－Ｓｉ ＴＦＴ。它可以有效地提高自对准αＳｉ：Ｈ ＴＦＴ的开态ＩＯＮ，其通断电流比ＩＯＮ／ＩＯＦＦ＞１０＾５。     

a—Si：H TFT自对准工艺的研究

实验研究了自对准结构的ａ－Ｓｉ：Ｈ ＴＦＴ的制备工艺，对其中关键的底部曝光和顶胶工艺进行了详细的研究和分析，对制备工艺和结构参数进行了合理的优化，成功地制备出自对准结构的ａ－Ｓｉ：Ｈ ＴＦＴ。对影响自对准结构ａ－Ｓｉ：Ｈ ＴＦＴ特性的主要因素进行了详细的分析，提出了一种新颖的双有源层结构的ａ－Ｓｉ：Ｈ ＴＦＴ，可以有效地改善ａ－Ｓｉ：Ｈ ＴＦＴ的开态特性，其通断电流比ＩＯＮ／ＩＯＦＦ〉１０＾５。     

自对准结构α－Si：HTFT特性的分析和研究

本文描述了用自对准工艺制各自对准结构的α－Ｓｉ：ＨＴＦＴ。从理论上分析了有源层α－Ｓｉ：Ｈ的厚度对α－Ｓｉ：ＨＴＦＴ特性的影响，据此提出一种新型的双有源层结构的α－ＳｉＴＦＴ。它可以有效地提高自对准α－Ｓｉ：ＨＴＦＴ的开态Ｉ＿（ＯＮ），其通断电流比Ｉ＿（ＯＮ）／Ｉ＿（ＯＦＦ）＞１０￣５。     

高性能a-Si∶HTFT开关器件的研制

介绍了 ａ Ｓｉ∶ Ｈ Ｔ Ｆ Ｔ 开关器件的有源层、栅绝缘层、欧姆接触层以及界面特性的研究工作。研制了 ａ Ｓｉ∶ Ｈ Ｔ Ｆ Ｔ 单管器件， 其开关电流比达到 ６ 个数量级， 为最终研制ａ Ｓｉ∶ Ｈ Ｔ Ｆ Ｔ Ａ Ｍ Ｌ Ｃ Ｄ 视频图像显示器奠定了坚实的基础。     

a—SiN：：H的退火自理及其对a—Si：HTFT性能与可靠性的影响

研究了ａ－ＳｉＮ：Ｈ的退火行为及其作为栅介质使用时，退火对ａ－Ｓｉ：ＨＴＦＴ工作特性和可靠性的影响，实验事实表明，在３８０℃以下的退火处理ａ－ＳｉＮ：Ｈ介电常数的变化呈单调上升趋势，对ａ－ＳｉＮ：Ｈ ＴＦＴ的工作特性和可靠性有明显的改善，温度进一步升高时，介电常数减小，ａ－Ｓｉ：ＨＴＦＴ的特性变坏。     

高性能a-Si:H TFT开关器件的研制

介绍了ａ－Ｓｉ：ＨＴＦＴ开关器件的有源层、栅绝缘层、欧接触层以及界面特性的研究工作。研制了ａ－Ｓｉ：ＨＴＦＴ单管器件,其开关电流达到６个数量级,为最终研制ａ－Ｓｉ：ＨＴＦＴＡＭＬＣＤ在奠定了坚实的基础。     

a—Si：H TFT电流—电压特性研究

本文发展了一种研究ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的新方法。基于局域态电荷密度解析统一模型，提出并深入分析了沟道区有效温度参数的概念，并由此推导出了ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的解析表达式。其理论值与实验值符合很好。该模型可用于ａ－Ｓｉ：Ｈ ＴＦＴ静态特性分析及其电路优化。     

a－SiN∶H的退火处理及其对a－Si∶H TFT性能与可靠性的影响

研究了ａ－ＳｉＮ：Ｈ的退火行为及其作为栅介质使用时，退火对ａ－Ｓｉ：ＨＴＦＴ工作特性和可靠性的影响．实验事实表明，在３８０℃以下的退火处理使ａ－ＳｉＮ：Ｈ介电常数的变化呈单调上升趋势，对ａ－Ｓｉ：ＨＴＦＴ的工作特性和可靠性有明显的改善，温度进一步升高时，介电常数减小，ａ－Ｓｉ：ＨＴＦＴ特性变坏．     

一种能有效抑制背光照影响的非晶硅薄膜晶体管

提出了一种能有效抑制背光照影响的非晶硅薄膜晶体管结构。详细地分析了源、漏电极接触区和沟通区内载流子的输运特性。论述了在背光照射下,这种结构的ＴＦＴ能有铲抑制关态电流上升的机理。研究了有源层ａ－Ｓｉ：Ｈ膜层厚度对ＴＦＴ关态电流和开态电流的影响。检测辽种结构ＴＦＴ在暗态和背照射下的静态特性。     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

a—SiNx：H薄膜对a—Si：H TFT阈值电压的影响

介绍了测定a－Si：HTFT闽值电压的实验方法。重点研究了改变a－SiNx：H薄膜淀积时反应气体NH3／SiH4流速比以及a－SiNx:H膜厚对a－Si：HTFT阈值电压的影响。对实验结果进行了分析。实验结果表明：a－Si:HTFT的阈值电压随a－SiNx：H的膜厚增加而增大；增大X－SiNx：H薄膜淀积时NH3／SiH4气体流速比，可明显减小a-Si:HTFT的阈值电压。     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Modeling of current-voltage characteristics for dual-gate amorphous silicon thin-film transistors considering deep Gaussian density-of-state distribution

Considering combination of the deep Gaussian and tail exponential distribution of DOS (density of states) instead of double exponentials empirically, a physics-based approximation has been developed to describe the behavior of the surface and centric potential as a function of applied voltage for DG a-Si:H TFT (amorphous silicon thin film transistor with dual gate). The resulting scheme provides a novel method for quickly evaluation of the inter-related potentials and is proved to offer better computational efficiency than other numerical alternatives. Based on these potentials, a compact drain current model accounting for the interaction factor has been proposed that followed. We show what parameters are truly required for accurately describing the I-V characteristic of DG a-Si:H TFT and just how qualitatively these parameters affect TFTs current. Model derivation also demonstrated an intuitive physical explanation for the gate-voltage dependent mobility as usually observed experimentally in these devices. Terms of potentials and current calculation are successively verified by comparison with numerical and the published experimental data.     

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors

In this paper, an analytical a-Si:H thin-film transistor (TFT) model based on surface potential is presented. Firstly, an explicit approximation for the surface potential as a function of terminal voltages is proposed. In the new analytical solution, simultaneously, the effects of localized trapped charges and free carriers are considered. Moreover, the complex iterative computation is eliminated in the solution. Comparing with the numerical results, the proposed solution shows a high accuracy for predicting the surface potential under various biases. Secondly, a charge sheet model is then developed for the analysis of DC characteristics of a-Si:H TFT. The improved model can describes all operation regions via an unique formula and it is verified by a reasonable agreement between the simulated results and the experimental data.     

High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications

A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is developed in this letter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts of source/drain metal and the sidewall of a-Si:H island edge. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility as high as 1.05 cm/sup 2//Vs, due to the enormous improvement in parasitic resistance. The impressively high performance of the proposed a-Si:H TFT provides the potential to apply foractive matrix liquid crystal display and active matrix organic light-emitting diode technology.     

Device analysis for a-Si:H thin-film transistors with organicpassivation layer

Two dimensional device analysis has been performed to explain the experimental drain current-gate voltage (I_D-V_GS) characteristics of hydrogenated amorphous silicon thin-film transistors with various passivation layers. The shift of the I_D-V_GS curve in the negative direction and the increase of S-factor (the inverse of subthreshold slope in logarithmic I_D-V_GS curve) can be explained well by introducing positive fixed charges and defect states in the back interface region. It was found that the positive fixed charge and the defect density of a-Si:H TFT with an organic passivation layer are higher than those of conventional a-Si:H TFT with a silicon-nitride (SiN_x) passivation layer. The simulation shows that the front and back interfaces interact and this explains why the passivation affects the device performance such as V_th and S-factor in a-Si:H TFTs     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V