Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication

For the first time, we demonstrate that a chaperonin protein lattice can be used as a template to assemble nanocrystal (NC) arrays for Flash memory fabrication. This provides a new approach that can incorporate different types of NCs from a colloidal suspension for Flash memory fabrication. Lead selenide and cobalt NC assemblies achieved through this method have a high density of 9.5times10¹¹/cm ² and 1.6times10¹²/cm², respectively, as well as good distribution uniformity. Devices exhibit promising Flash memory functions, with a flatband shift of 0.5 under 8-V operation, endurance >10⁵ cycles, and retention time >10⁴ s     

Device characteristics of 0.35 μm P-channel DINOR flash memoryusing band-to-band tunneling-induced hot electron (BBHE)programming

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-μm-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 μs/512 byte) and a low current consumption of less than 250 μA were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10⁶ program/erase cycles, and window narrowing and G_m degradation were found to be very small even after 10⁶ cycles. It is thought that the BBHE injection point contributes to the G _m stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories     

Low-threshold room-temperature operation of injectorless quantum-cascade lasers: influence of doping density

The influence of the doping density in the active sections of InP-based injectorless quantum cascade lasers, emitting at 6.8 mum, is investigated. The doping sheet density is varied in the range 2.5-8.6times10¹⁰ cm^-2. Lasing is observed in the whole range, with a threshold current density as low as 1.2 kA/cm² at 300 K for the smallest doping sheet density of 2.5times10 ¹⁰ cm^-2. Further improvement has been made by additionally increasing the number of periods in the active region from 40 to 60. With the same doping level of 2.5times10¹⁰ cm^-2 record low threshold current densities of 0.73 kA/cm² at 300 K were achieved     

Erbium-Based Photonic Flip-Flop Memories: Model and Experimental Validation

Operating principle for a flip-flop memory cell based on erbium-doped devices is presented. A complete model for memory dynamics is introduced taking into account, at the same time, for memory writing, reading, and erasing. Simple equations are found relating writing, spontaneous and stimulated erasing times to device physical parameters, signals wavelength and power. In principle, for example, increasing writing and erasing energies at the appropriate wavelength it is possible to dramatically reduce transition times. Extinction ratio (ER) is also determined as a function of host medium, and signals properties. An optimization technique is proposed for erasing signal design in order to guarantee maximum ER. Numerical example are provided for Er and Er-Yb doped fibers whose doping ion density is rho = 1.1413middot10²⁴ ions/m³, and 2.0 middot10²⁵ ions/m³, respectively. Finally, an experimental demonstration giving an Er higher than 5 and 16 dB for the two fibers, respectively, is provided and discussed.     

Time Evolution of the Screening of Piezoelectric Fields in InGaN Quantum Wells

We have measured the time response of the emission spectra of In _0.07Ga_0.93N quantum wells with widths of 2, 3, and 4nm in GaN following pulsed optical excitation. We observe a blue shift of the emission peak during the excitation and a subsequent red shift as the carriers recombine in the 3- and 4-nm wells, and a negligible shift for the 2-nm well. Using a comprehensive theory we are able to fit both the time evolution of the peak emission energy and the integrated emission intensity. The shift of the emission peak (by about 17 meV) arises from the balancing of the change in screening of the internal piezoelectric field as the carrier density changes and bandgap renormalization. We have projected the calculations to quantify the degree of screening at typical threshold carrier densities. At transparency we estimate carrier densities of 4.3times10¹⁶ m^-2 and 4.8times10¹⁶ m^-2 for the 4- and 3-nm wells, respectively, which reduce the internal piezoelectric field in the well to 0.97times10⁸ (4 nm) and 1.03times10 ⁸ (3 nm) Vmiddotm^-1 compared with the unscreened value of about 1.23times10⁸ Vmiddotm^-1. Thus, a substantial field remains in these wells under laser conditions. We find that this partially screened field is beneficial in reducing the threshold current compared with that of a square well for modal gains up to about 150 cm^-1     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

Incoherent annealing of implanted layers in GaAs

Incoherent light from filament lamps focused by elliptical mirrors has been used to activate implanted layers in GaAs. 4 × 10¹⁴Si⁺cm^-2and 2 × 10¹⁴Zn⁺cm^-2implants were annealed with Si3N4deposited by CVD at 400°C providing a surface protective layer. By taking advantage of the focusing properties of elliptical mirrors, most of the emitted light could be concentrated onto the GaAs to give annealing times × 1 sec. Differential Hall measurements show peak carrier concentrations of 6.5 × 10¹⁸cm^-3and 50% activation for the n+ layers. The Zn implants were completely activated and doped to ∼ 2 × 10¹⁹cm^-3. These results, together with the short annealing times, suggest the present approach to be an attractive alternative to both laser and conventional thermal annealing.     

Biclique cryptanalysis on lightweight block ciphers I-PRESENT-80 and I-PRESENT-128

I-PRESENT was a lightweight SPN block cipher for resource-constraint environments such as RFID tags and sensor networks.The biclique structures of I-PRESENT with sieve-in-the-middle technique was an constracted.The biclique cryptanalysis schemes on full-round I-PRESENT-80 and I-PRESENT-128 were proposed for the first time.The results show that the data complexity of the biclique cryptanalysis on I-PRESENT-80 and I-PRESENT-128 is 2 ²⁶ and 2³⁶ chosen ciphertexts respectively，and the time complexity on them is 2 ^79.48 and 2 ^127.33 encryptions respectively.The time and data complexity are better than that of the exhaustive attack.In addition,the time complexity on them can be reduced to 2 ^78.61 and 2^126.48 encryptions by using related-key technology of I-PRESENT.     

Silicon nano-particles in SiO2 sol–gel film for nano-crystal memory device applications

A novel 2-bit nano-silicon based non-volatile memory is proposed to double memory density. The thin film structure exhibits two conduction states (ON and OFF) at different voltages and has a cost-effective structure. The structure utilizes the good electrical properties of fluorinated SiO₂ thin films, together with the bi-stable properties conferred by the nano-silicon particles therein embedded. A polymeric layer of 8-hydroxyquinoline aluminum salt (Alq3) further deposited on the top of the nano-particle layer through chemical evaporation and a silver paste contact determines the final structure. The positive 0–15 V scan reveals two discontinuities with an ON/OFF ratio of 10⁴–10⁵ (2–4 V) and OFF/ON of 10³ (12.5–13.0 V). The reverse scan displays again two distinct thresholds, range of 10.5–11.0 V (ON/OFF ratio 10⁻³), respectively, 0.5 V (OFF/ON ratio 10⁻⁵–10⁻⁴).     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made     

Vibration-vibration energy transfer in the v3mode of CO2

The vibration-vibration energy transfer of CO2gas initially excited to the first asymmetric stretch level (00⁰1) has been observed. Collisional pumping to the (01¹1) combination level is measured by monitoring the fluorescence due to the (01¹1) → (01¹0) band. The rate constant for the process: CO2(01¹1) + CO2(00⁰0) → CO2(00⁰1) + CO2(01¹0) is found to be(5.3 pm 1) times 10^{6}s^-1torr^-1.     

Impact of Nonlinear Memory Effects on Digital Communications in a Klystron

Nonlinear memory effects in a klystron and their impact on digital communications are investigated using a time-domain physics-based model. The simulation results are compared to an idealized block model based on the frequency response and amplitude/phase drive curves typically used in system design with vacuum electronic amplifiers. Significant departures in transient behavior are noted in the physics-based model in comparison to the block model when the klystron is at or near saturation, provided that the signal bandwidth is simultaneously large ( ges ~65% of the klystron output cavity bandwidth). Such nonlinear memory effects exist for pure amplitude, pure phase, and mixed transients of both the step and ramp variety. The effects of these nonlinear phenomena on 16-state phase-shift keying (16-PSK) digital communications waveforms (with preequalized symbols) are examined using symbol constellation diagrams and symbol error rate (SER) plots. Operation at saturation with signal bandwidths of 32%, 65%, and 93% of the klystron output cavity bandwidth, for a bit-energy-based signal-to-noise ratio of 18 dB, yields SER values of 2.0 times 10^-5, 2.3 times 10^-4, and 2.7 times 10^-3 , respectively, in comparison to the ideal 16-PSK value of 1.1 times 10^-5.     

On the design of low-density parity-check codes within 0.0045 dB ofthe Shannon limit

We develop improved algorithms to construct good low-density parity-check codes that approach the Shannon limit very closely. For rate 1/2, the best code found has a threshold within 0.0045 dB of the Shannon limit of the binary-input additive white Gaussian noise channel. Simulation results with a somewhat simpler code show that we can achieve within 0.04 dB of the Shannon limit at a bit error rate of 10^-6 using a block length of 10⁷     

An 80-ns 1-Mb flash memory with on-chip erase/erase-verifycontroller

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ². The die area is 32.3 mm². An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor     

Strong increase of the derivative of the carrier-induced indexchange of semiconductor lasers at low injected carrier density

The carrier-induced index change of a semiconductor laser was measured for injected carrier density ranging from 3 × 10¹⁶ cm^-3 to 2 × 10¹⁸ cm^-3. A strong nonlinear behavior between index change and carrier density is observed. The derivative of the index change versus carrier density at low carrier density can be 15 times larger than the derivative of the index change at high carrier density     

Nine-state resonant tunneling diode memory

The authors demonstrate an epitaxial series combination of eight pseudomorphic AlAs/In_0.53Ga_0.47As/InAs resonant tunneling diodes (RTDs) grown by molecular beam epitaxy on InP. This series RTD produces an eight-peak multiple negative differential resistance characteristic with a peak-to-valley current ratio (PVR) exceeding 2 per peak at a peak current density of approximately 6 kA/cm ². Hysteresis in the current-voltage characteristic is reduced by uniformly Si doping the double-barrier resonant tunneling region at a density of 5×10¹⁶ cm^-3. Using this multiple-peak RTD in series with a field-effect transistor load, a nine-state multivalued memory circuit is demonstrated     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm² middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface     

A 144-Mb, eight-level NAND flash memory with optimized pulsewidthprogramming

We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-μm CMOS process, resulting in a 104.2-mm² die size and a 1.05-μm² effective cell size