Improvement of voltage linearity in high-/spl kappa/ MIM capacitors using HfO/sub 2/-SiO/sub 2/ stacked dielectric

It is demonstrated that the voltage coefficients of capacitance (VCC) in high-/spl kappa/ metal-insulator-metal (MIM) capacitors can be actively engineered and voltage linearity can be significantly improved maintaining high capacitance density, by using a stacked insulator structure of high-/spl kappa/ and SiO/sub 2/ dielectrics. A MIM capacitor with capacitance density of 6 fF/spl mu/m/sup 2/ and quadratic VCC of only 14 ppm/V/sup 2/ has been demonstrated together with excellent frequency and temperature dependence (temperature coefficients of capacitance of 54 ppm /spl deg/C) as well as low leakage current of less than 10 nA/cm/sup 2/ up to 4 V at 125 /spl deg/C.     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

Integrated high-/spl kappa/ (/spl kappa/ /spl sim/19) MIM capacitor with Cu/low-/spl kappa/ interconnects for RF application

We demonstrate a high-performance metal-high /spl kappa/ insulator-metal (MIM) capacitor integrated with a Cu/low-/spl kappa/ backend interconnection. The high-/spl kappa/ used was laminated HfO/sub 2/-Al/sub 2/O/sub 3/ with effective /spl kappa/ /spl sim/19 and the low-/spl kappa/ dielectric used was Black Diamond with /spl kappa/ /spl sim/2.9. The MIM capacitor (/spl sim/13.4 fF//spl mu/m/sup 2/) achieved a Q-factor /spl sim/53 at 2.5 GHz and 11.7 pF. The resonant frequency f/sub r/ was 21% higher in comparison to an equivalently integrated Si/sub 3/N/sub 4/-MIM capacitor (/spl sim/0.93 fF//spl mu/m/sup 2/) having similar capacitance 11.2 pF. The impacts of high-/spl kappa/ insulator and low-/spl kappa/ interconnect dielectric on the mechanism for resonant frequency improvement are distinguished using equivalent circuit analysis. This letter suggests that integrated high-/spl kappa/ MIM could be a promising alternative capacitor structure for future high-performance RF applications.     

Very high density RF MIM capacitors (17 fF//spl mu/m/sup 2/) using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectrics

Using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectric, we have obtained record high MIM capacitance density of 17 fF//spl mu/m/sup 2/ at 100 kHz, small 5% capacitance reduction to RF frequency range, and low leakage current density of 8.9/spl times/10/sup -7/ A/cm/sup 2/. In combination of both high capacitor density and low leakage current density, a very low leakage current of 5.2/spl times/10/sup -12/ A is calculated for a typical large 10 pF capacitor used in RF IC that is even smaller than that of a deep sub-/spl mu/m MOSFET. This very high capacitance density with good MIM capacitor characteristics can significantly reduce the chip size of RF ICs.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

A novel program-erasable high-/spl kappa/ AlN-Si MIS capacitor

We demonstrate a programmable-erasable MIS capacitor with a single layer high-/spl kappa/ AlN dielectric on Si having a high capacitance density of /spl sim/5 fF//spl mu/m/sup 2/. It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al/sub 2/O/sub 3/, AlON, or other known high-/spl kappa/ dielectric capacitors, where the threshold voltage (V/sub th/) shifts continuously with voltage. This device exhibits good data retention with a V/sub th/ change of only 0.06 V after 10 000 s.     

A high-density MIM capacitor (13 fF//spl mu/m/sup 2/) using ALD HfO/sub 2/ dielectrics

Metal-insulator-metal (MIM) capacitors with different HfO/sub 2/ thickness have been investigated. The results show that both the capacitance density and voltage coefficients of capacitance (VCCs) increase with decreasing HfO/sub 2/ thickness. In addition, it is found that the VCCs decrease logarithmically with increasing thickness. Furthermore, the MIM capacitor with 10-nm HfO/sub 2/ shows a record high capacitance density of 13 fF//spl mu/m/sup 2/ and a VCC of 607 ppm/V, which can meet the requirement of the International Technology Roadmap for Semiconductors. It can also provide a low leakage current of 5.95 /spl times/ 10/sup -8/A/cm/sup 2/ at room temperature at 1 V, low tangent values below 0.05, and a small frequency dependence. These results indicate that the devices are suitable for use in silicon integrated circuit applications.     

Characterization of accumulation layer capacitance for extracting data on high-/spl kappa/ gate dielectrics

A new parameter extraction technique has been outlined for high-/spl kappa/ gate dielectrics that directly yields values of the dielectric capacitance C/sub di/, the accumulation layer surface potential quotient, /spl beta//sub acc/, the flat-band voltage, the surface potential /spl phi//sub s/, the dielectric voltage, the channel doping density and the interface charge density at flat-band. The parallel capacitance, C/sub p/(=C/sub sc/+C/sub it/), was found to be an exponential function of /spl phi//sub s/ in the strong accumulation regime, for seven different high-/spl kappa/ gate dielectrics. The slope of the experimental lnC/sub p/(/spl phi//sub s/) plot, i.e., |/spl beta//sub acc/|, was found to depend strongly on the physical properties of the high-/spl kappa/ dielectric, i.e., was inversely proportional to [(/spl phi//sub b/m/sup *//m)/sup 1/2/K/C/sub di/], where /spl phi//sub b/ is the band offset, and m/sup */ is the effective tunneling mass. Extraction of /spl beta//sub acc/ represented an experimental carrier confinement index for the accumulation layer and an experimental gate-dielectric direct-tunneling current index. /spl beta//sub acc/ may also be an effective tool for monitoring the effects of post-deposition annealing/processing.     

RF, DC, and reliability characteristics of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for Si RF IC applications

High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF//spl mu/m/sup 2/) up to 20 GHz, low leakage current of 4.9/spl times/10/sup -8/ A/cm/sup 2/ at 2 V and 125/spl deg/C, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (/spl alpha/) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

MOS capacitors on epitaxial Ge-Si/sub 1-x/Ge/sub x/ with high-/spl kappa/ dielectrics using RPCVD

We report the successful growth of MOS capacitor stacks with low temperature strained epitaxial Ge or Si/sub 1-x/Ge/sub x/(x=0.9) layer directly on Si substrates, and with HfO/sub 2/(EOT=9.7 /spl Aring/) as high-/spl kappa/ dielectrics, both using a novel remote plasma-assisted chemical vapor deposition technique. These novel MOS capacitors, which were fabricated entirely at or below 400/spl deg/C, exhibit normal capacitance-voltage and current-voltage characteristics.     

Evidence and understanding of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors outperforming sandwich counterparts

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.     

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

Lanthanide (Tb)-doped HfO/sub 2/ for high-density MIM capacitors

A high-density metal-insulator-metal (MIM) capacitor with a lanthanide-doped HfO/sub 2/ dielectric prepared by physical vapor deposition (PVD) is presented for the first time. A significant improvement was shown in both the voltage coefficient of capacitance (VCC) and the leakage current density of MIM capacitor, yet the high capacitance density of HfO/sub 2/ dielectrics was maintained by achieving the doping of Tb with an optimum concentration in HfO/sub 2/. This technique allows utilizing thinner dielectric film in MIM capacitors and achieving a capacitance density as high as 13.3 fF//spl mu/m/sup 2/ with leakage current and VCC values that fully meet requirements from year 2005 for radio frequency (RF) bypass capacitors applications.     

Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb/sub 2/O/sub 5/) with HfO/sub 2//Al/sub 2/O/sub 3/ barriers

A high capacitance density (C/sub density/) metal-insulator-metal (MIM) capacitor with niobium pentoxide (Nb/sub 2/O/sub 5/) whose k value is higher than 40, is developed for integrated RF bypass or decoupling capacitor application. Nb/sub 2/O/sub 5/ MIM with HfO/sub 2//Al/sub 2/O/sub 3/ barriers delivers a high C/sub density/ of >17 fF//spl mu/m/sup 2/ with excellent RF properties, while maintaining comparable leakage current and reliability properties with other high-k dielectrics. The capacitance from the dielectric is shown to be stable up to 20 GHz, and resonant frequency of 4.2 GHz and Q of 50 (at 1 GHz) is demonstrated when the capacitor is integrated using Cu-BEOL process.     

The effect of IrO/sub 2/--IrO/sub 2/--Hf--LaAlO/sub 3/ gate dielectric on the bias-temperature instability of 3-D GOI CMOSFETs

We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-/spl kappa//Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 /spl mu/m CMOSFETs. The devices used IrO/sub 2/--IrO/sub 2/-Hf dual gates and a high-/spl kappa/ LaAlO/sub 3/ gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-/spl kappa//GOI p-and n-MOSFETs displayed threshold voltage (V/sub t/) shifts of 30 and 21 mV after 10 MV/cm, 85/spl deg/C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-/spl kappa/-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.