Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

We investigate in this paper board-level drop reliability of chip-scale packages subjected to JEDEC drop test condition B, which features an impact pulse profile with a peak acceleration of 1500G and a pulse duration of 0.5 ms. Effects of Sn–Ag–Cu or Sn–Pb solder joint compositions, fluxes, and substrate pads with Ni/Au surface finish or OSP coating on the drop reliability of the board-level test vehicle are compared. Locations and modes of the failed solder joints are examined using the dye stain test. The results indicate that solder joints with a low Ag weight content and substrate pads with OSP coating both enhance the drop resistance of the board-level test vehicle.     

Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level chip-scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L₉ (3⁴) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.     

Reliability study of board-level lead-free interconnections under sequential thermal cycling and drop impact

The sequential thermal cycling (TC) and drop impact test are more reasonable to evaluate the reliability of lead-free solder interconnections compared with separate TC test or drop impact test. In this paper, sequential TC (−40 °C/125 °C, 13 min of soak time, 12 min of dwell time, totally 50 min of cycle time) and drop impact test (a sine impact pulse with a peak acceleration of 1500g and a duration time of 0.5 ms) were conducted to study the failure mechanism of solder interconnections under sequential TC and drop impact test. The TC load has larger effect on the Cu/solder interface at the PCB side than that of Ni (P)/solder interface at the component side. For the thermally cycled samples, the failure location of solder interconnections under drop impact has changed from initiation and propagation along the thin reaction layer (mode 1) between intermetallic compound (IMC) layer and Ni (P) pad at the component side to initiation at the bulk solder and propagation along the Cu₃Sn IMC layer (mode 2) or entirely through the bulk solder (mode 3) at the PCB side. The failure mechanism has also changed from the entirely brittle crack to the mixture of fatigue crack and brittle crack.     

Consideration of temperature and current stress testing on flip chip solder interconnects

This work discusses the experimental set-up and data interpretation for high temperature and current stress tests of flip chip solder joints using the four-point Kelvin measurement technique. The single solder joint resistance responses are measured at four different four-point Kelvin structure locations in a flip chip package. Various temperatures (i.e., 125–165 °C) and electric current (i.e., 0.6–1.0 A) test conditions are applied to investigate the solder joint resistance degradation behavior and its failure processes. Failure criterion of 20% and 50% joint resistance increases, corresponding to solder and interfacial voiding, are employed to evaluate the solder joint electromigration reliability. The absolute resistance value is substantially affected by the geometrical layout of the metal lines in the four-point Kelvin structure, and this is confirmed by finite element simulation.Different current flow directions and strengths yielded different joint resistance responses. The anode joint, where electrons flow from the die to the substrate, usually measured an earlier resistance increase than the cathode joint, where electrons flow in the opposite direction. The change in measured joint resistances can be related to solder and interfacial voiding in the solder joint except for ±1 A current load, where resistance drop mainly attributed to the broken substrate Cu metallization as a result of “hot-spot” phenomenon. The solder joint temperature increases above the oven ambient temperature by ～25 °C, ～40 °C and ～65 °C for 0.6 A, 0.8 A and 1.0 A stress current, respectively. It is found that two-parameter log-normal distribution gives a better lifetime data fitting than the two-parameter Weibull distribution. Regardless of failure criterion used, the anode joint test cells usually calculated a shorter solder joint mean life with a lower standard variation of 0.3–0.6, as compared to the cathode joint test cells with a higher standard variation of 0.8–1.2. For a typical flip chip solder joint construction, electromigration reliability is mainly determined by the under bump metallization consumption and dissolution, with intermetallic compound formation near the die side of an anode joint.     

板级跌落碰撞下无铅焊点的可靠性研究

文中引入一块不同于JEDEC标准测试板的圆形测试板,探究板级跌落碰撞下无铅焊点的可靠性.首先做模态试验了解测试板的动力学特性,接着做跌落测试,同时测量板的应变和加速度历程.并用ABAQUS软件进行模拟,模拟焊点在跌落碰撞条件下焊点的应力应变等.结果表明有限元模拟得到的应变、板中心的加速度响应和试验吻合,而且用模拟预测的失效焊点的位置与试验一致.失效模式是靠近封装一侧的金属间化合物(IMC)界面的脆性断裂.     

Evaluation on Influencing Factors of Board-Level Drop Reliability for Chip Scale Packages (Fine-Pitch Ball Grid Array)

Board-level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this study, drop test of printed circuit boards (PCBs) with a four-screw support condition was conducted for a 15 mm times 15 mm fine-pitch ball grid array (FBGA) package assembly with solder ball compositions of 36Pb-62Sn-2Ag and Sn-4Ag-0.5Cu on printed circuit board (PCB) surface finishes of organic solderability preservative, electroless nickel immersion gold, and immersion tin. Finite element modeling of the FBGA assembly was performed to study the stress-strain behavior of the solder joints during drop test. The drop test results revealed a strong influence of different intermetallic compound formation on soldered assemblies drop durability. The lead-based solder supersedes the lead-free composition regardless of the types of surface finish. Joints on organic solderability preservative were found to be strongest for each solder type. Other factors affecting drop reliability such as component location on the board and thermal cycling aging effects are reported. Finite element modeling results showed that a solder joint is more prone to failure on the PCB side, and the predicted solder joint stresses are location dependent. Predicted failure sites based on simulation results are consistent with experimental observations.     

Reliability of lead-free interconnections under consecutive thermal and mechanical loadings

To simulate more realistically the effects of strains and stresses on the reliability of portable electronic products, lead-free test assemblies were thermally cycled (−45°C/+125°C, 15-min. dwell time, 750 cycles) or isothermally annealed (125°C, 500 h) before the standard drop test. The average number of drops to failure increased when the thermal cycling was performed before the drop test (1,500 G deceleration, 0.5 ms half-sine pulse). However, the difference was not statistically significant due to the large dispersion in the number of drops to failure of the assemblies drop tested after the thermal cycling. On the other hand, the average number of drops to failure decreased significantly when the isothermal annealing was carried out before the drop test. The failure analysis revealed four different failure modes: (1) cracking of the reaction layers on either side of the interconnections, (2) cracking of the bulk solder, (3) mixed mode of component-side intermetallic and bulk solder cracking, and (4) voidassisted cracking of the component-side Cu₃Sn layer. The assemblies that were not thermally cycled or annealed exhibited only type (1) failure mode. The interconnections that were thermally cycled before the drop test failed by mode (2) or mode (3). The drop test reliability of the thermally cycled interconnections was found to depend on the extent of recrystallization generated during the thermal cycling. This also explains the observed wide dispersion in the number of drops to failure. On the other hand, the test boards that were isothermally annealed before the drop testing failed by mode (4).     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

3D FEM Simulations of Drop Test Reliability on 3D-WLP: Effects of Solder Reflow Residual Stress and Molding Resin Parameters

Numerous three-dimensional (3D) packaging technologies are currently used for 3D integration. 3D-wafer level package (3D-WLP) appears to be a way to keep increasing the density of the microelectronic components. The reliability of 3D components has to be evaluated on mechanical demonstrators with daisy chains before real production. Numerical modeling is acknowledged as a very efficient tool for design optimization. In this paper, 3D finite-elements calculations are carried out to analyze the effects of molding resin’s mechanical properties and thickness on the 3D component’s dynamic response under drop loading conditions. Residual stress generated by solder reflow is also discussed. The influences of residual stresses on the numerical estimation of the component behavior during drop loading are studied. Solder reflow residual stresses have an impact on solder plastic strain and die equivalent stress calculations. We have compared the result of two numerical drop test models. Stress-free initial conduction is introduced for the first model. Solder reflow residual stresses are considered as the initial condition for the second drop test model. Quantitative and qualitative comparisons are carried out to show the effect of residual stress in drop test calculations. For the effect of molding resin thickness on the component behavior under drop loading, the stress-free initial condition is considered. The effect of the molding resin’s thickness on critical area location is discussed. The solder bump maximum plastic shear strain and the silicon die maximum equivalent stress are used as reliability criteria. Numerical submodeling techniques are used to increase calculation accuracy. Numerical results have contributed to the design optimization of the 3D-WLP component.     

Experimental analysis of Sn-3.0Ag-0.5Cu solder joint board-level drop/vibration impact failure models after thermal/isothermal cycling

Sn-3.0Ag-0.5Cu board-level lead-free solder joint drop (1000g, 1 ms)/vibration (15g, 25–35 Hz) reliability after thermal (− 40–125 °C, 1000 cycle)/isothermal (150 °C, 500 h) cycling was reported in this study. The failure performance of solder joint and testing life were analyzed under design six testing conditions (1. Single drop impact, 2. Order thermal cycling and drop impact, 3. Order isothermal cycling and drop impact, 4. Single vibration 5. Order thermal cycling and vibration 6. Order isothermal cycling and vibration). The results revealed that the pre-cracks initiation during thermal cycling do not affect the solder joint drop impact reliability, but decrease the vibration reliability. The formation of voids weaken both drop and vibration reliability of solder joint. After thermal cycling, the crack initiated from β-Sn near IMC layer, and continued propagation through the same path when under second in order vibration impact. But propagation path turn to IMC layer when under second in order drop impact. The drop life increases from 41 times to 49 times, and vibration life decrease from 77 min to 45 min. After isothermal cycling, the formation of voids let the cracks occurred at IMC layer under second in order no matter drop impact or vibration. The drop and vibration life is 19 times and 62 min respectively.     

Evaluation of board-level reliability of electronic packages under consecutive drops

In general, the drop reliability of a board-level electronic package is characterized by the number of drops to failure according to a certain failure criterion. This implies that damage of solder joints evolves during each drop and eventually leads to failure. Development of a numerical method capable of obtaining accumulated stresses and strains under consecutive drop conditions is therefore in need because without these damage factors, accurate predictions for the board-level drop reliability of electronic packages are unattainable. We implement in this paper the support excitation scheme incorporated with the implicit time integration scheme to study transient structural responses of a board-level chip-scale package subjected to consecutive drops. Accumulated stresses, plastic strains, and plastic strain energy densities on the solder joints under repetitive drop impacts are investigated.     

Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn–3.8Ag–0.7Cu and Eutectic SnPb Solders

High strain-rate drop impact tests were performed on ball grid array (BGA) packages with solder compositions of (in wt%) Sn-3.8Ag-0.7Cu (SnAgCu) and eutectic Sn-37Pb (SnPb). Solder balls were joined to the metallizations of plated Ni on the device side and plated Cu on the board side. The BGA packages were tested at 1500 g within 0.5 ms, resulting in an imposed bending strain of 0.2-0.3%. Both SnAgCu and SnPb joints failed at the interface at the device side but the detailed failure morphology differed significantly. The crack location for the eutectic SnPb was primarily through the solder and seldom extended through an entire bump. The SnPb joints also exhibited bulk solder deformation. The SnAgCu joints showed extremely brittle behavior with an interfacial failure at the (Ni,Cu)₃Sn₄ intermetallics/Ni under bump metallization (UBM) interface. The strain rate sensitivity of bulk solder defines the drop test performance and the eutectic SnPb solder showed better drop impact performance due to a less strain rate sensitivity     

Reliability and failure analysis of SAC 105 and SAC 1205N lead-free solder alloys during drop test events

The purpose of this study is to establish a predictive fatigue life model for SAC 105 (Sn-1.0Ag-0.5Cu) and SAC 1205N (Sn-1.2Ag-0.5Cu with nickel) lead-free solder alloys. A simulation model approach was developed to investigate the stress and strain of the solder joint during drop tests. A Joint Electronic Device Engineering Council (JEDEC) Condition B drop test was simulated. This test is characterized by a 1500g peak acceleration for an impulse duration of 0.5 ms. At the point of impact during the drop test, the deformation of the printed circuit board (PCB) via bending and mechanical shocks can cause joint cracks in the solder. To establish a predictive model for the 10% fatigue life of the lead-free solder joint under drop test conditions, the study was conducted in three main phases: material analysis of the lead-free solder alloy, the drop test model, and the 10% fatigue life analysis. Tensile tests of SAC 105 and SAC 1205N were used to examine the elastic and plastic behavior of the solder alloy mechanism. Simulations and drop tests were performed to investigate the failure of the microelectronic package resulting from the drop test. The predictive fatigue life models of SAC 105 and SAC 1205N were validated by the experimental results with satisfactory accuracy.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Electromigration Reliability and Morphologies of Cu Pillar Flip-Chip Solder Joints with Cu Substrate Pad Metallization

The Cu pillar is a thick underbump metallurgy (UBM) structure developed to alleviate current crowding in a flip-chip solder joint under operating conditions. We present in this work an examination of the electromigration reliability and morphologies of Cu pillar flip-chip solder joints formed by joining Ti/Cu/Ni UBM with largely elongated ∼62 μm Cu onto Cu substrate pad metallization using the Sn-3Ag-0.5Cu solder alloy. Three test conditions that controlled average current densities in solder joints and ambient temperatures were considered: 10 kA/cm² at 150°C, 10 kA/cm² at 160°C, and 15 kA/cm² at 125°C. Electromigration reliability of this particular solder joint turns out to be greatly enhanced compared to a conventional solder joint with a thin-film-stack UBM. Cross-sectional examinations of solder joints upon failure indicate that cracks formed in (Cu,Ni)₆Sn₅ or Cu₆Sn₅ intermetallic compounds (IMCs) near the cathode side of the solder joint. Moreover, the ~52-μm-thick Sn-Ag-Cu solder after long-term current stressing has turned into a combination of ~80% Cu-Ni-Sn IMC and ~20% Sn-rich phases, which appeared in the form of large aggregates that in general were distributed on the cathode side of the solder joint.     

Drop impact reliability of edge-bonded lead-free chip scale packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Computational Assessment of the Effects of Temperature on Wafer-Level Component Boards in Drop Tests

The drop reliability of wafer-level chip-scale package (WL-CSP) component boards used in portable devices was studied by employing mechanical shock loads (JESD22-B111 standard) at different temperatures. The drop tests were carried out at room temperature (23 $^{circ}{hbox {C}}$), 75 $^{circ}{hbox {C}}$, 100 $^{circ}{hbox {C}}$, and 125 $^{circ}{hbox {C}}$. The elevated temperatures were achieved by integrated heater elements in the components. The number of drops-to-failure increased significantly with increasing temperature. The physical failure analysis revealed that the outermost solder interconnections at the four corners of the components failed from the component side. At room temperature, the cracks propagated solely along the intermetallic layers but the increase of testing temperature progressively changed their propagation paths from the intermetallic layers into the bulk solder. Since the temperature 1) decreases the strength and elastic modulus of solders, 2) diminishes the stiffness of printed wiring boards, and 3) introduces thermally induced stresses, the finite-element method was employed to evaluate their combined effects. The calculations showed that due to the increases in testing temperature, the peeling stress is reduced markedly, while the equivalent plastic strain is only slightly increased at the interfacial regions of the solder interconnections. The reduction of the stresses increases the proportion of the bulk solder cracking relative to the cracking of the intermetallic layers and therefore the number of drops-to-failure increases as a function of increasing test temperature.      

Failure mechanisms of lead-free chip scale package interconnections under fast mechanical loading

The reliability of chip scale package (CSP) components against mechanical shocks has been studied by employing statistical, fractographic, and microstructural research methods. The components having high tin (Sn0.2Ag0.4Cu) solder bumps were reflow soldered with the Sn3.8Ag0.7Cu (wt.%) solder paste on Ni(P)|Au- and organic solderability preservative (OSP)-coated multilayer printed wiring boards (PWBs), and the assemblies were subjected to the standard drop test procedure. The statistically significant difference in the reliability performance was observed: the components soldered on Cu|OSP were more reliable than those soldered on Ni(P)|Au. Solder interconnections on the Cu|OSP boards failed at the component side, where cracks propagated through the (Cu,Ni)₆Sn₅ reaction layer, whereas interconnections on the Ni(P)|Au boards failed at the PWB side exhibiting the brittle fracture known also as “black pad.” In the first failure mode, which is not normally observed in thermally cycled assemblies, cracks propagate along the intermetallic layers due to the strong strain-rate hardening of the solder interconnections in drop tests. Owing to strain-rate hardening, the stresses in the solder interconnections increase very rapidly in the corner regions of the interconnections above the fracture strength of the ternary (Cu,Ni)₆Sn₅ phase leading to intermetallic fracture. In addition, because of strain-rate hardening, the recrystallization of the as-soldered microstructure is hindered, and therefore the network of grain boundaries is not available in the bulk solder for cracks to propagate, as occurs during thermal cycling. In the black pad failure mode, cracks nucleate and propagate in the porous NiSnP layer between the columnar two-phase (Ni₃P+Sn) layer and the (Cu,Ni)₆Sn₅ intermetallic layer. The fact that the Ni(P)|Au interconnections fail at the PWB side, even though higher stresses are generated on the component side, underlines the brittle nature of the reaction layer.     

Numerical study of ductile failure morphology in solder joints under fast loading conditions

A numerical study is undertaken to investigate solder joint failure under fast loading conditions. The finite element model assumes a lap-shear testing configuration, where the solder joint is bonded to two copper substrates. A progressive ductile damage model is incorporated into the rate-dependent elastic-viscoplastic response of the tin (Sn)–silver (Ag)–copper (Cu) solder alloy, resulting in the capability of simulating damage evolution leading to eventual failure through crack formation. Attention is devoted to deformation under relative high strain rates (1–100 s⁻¹), mimicking those frequently encountered in drop and impact loading of the solder points. The effects of applied strain rate and loading mode on the overall ductility and failure pattern are specifically investigated. It is found that, under shear loading, the solder joint can actually become more ductile as the applied strain rate increases, which is due to the alteration of the crack path. Failure of the solder is very sensitive to the deformation mode, with a superimposed tension or compression on shear easily changing the crack path and tending to reduce the solder joint ductility.