Cascode混沌电路负阻模型与电路设计

针对Cascode结构振荡器进行研究,通过理论推导和分析,给出两级负阻提升的通用模型,该模型可以被广泛应用于混沌电路设计中,实际电路设计时可以用合适的负阻电路单元替代两级结构中的下级部分,实现电路负阻的提升。仿真设计结果表明,基于该模型设计的混沌电路的混沌振荡基频f0为4.2 GHz,f0/fT值达到0.46,较经典单级电路有较大提升。     

30GHz PHEMT振荡器

介绍了一种30GHz单片压控振荡器的设计、制作和性能.该芯片采用PHEMT工艺制作,电路基于负阻匹配共源网络结构设计.根据PHEMT器件的小信号S参数和直流I-V参数,提取出该器件的Modified-MaterkaFET模型参数,变容二极管由共源-漏晶体管来完成,并通过栅压来控制其容值.测试该电路振荡频率为30.12GHz,输出功率达到12.5dBm,调谐带宽大于150MHz.振荡器的测试结果与理论设计结果基本吻合.     

30GHz PHEMT振荡器

介绍了一种30GHz单片压控振荡器的设计、制作和性能.该芯片采用PHEMT工艺制作,电路基于负阻匹配共源网络结构设计.根据PHEMT器件的小信号S参数和直流I-V参数,提取出该器件的Modified-MaterkaFET模型参数,变容二极管由共源-漏晶体管来完成,并通过栅压来控制其容值.测试该电路振荡频率为30.12GHz,输出功率达到12.5dBm,调谐带宽大于150MHz.振荡器的测试结果与理论设计结果基本吻合.     

30GHz PHEMT振荡器

介绍了一种30GHz 单片压控振荡器的设计、制作和性能. 该芯片采用PHEMT工艺制作，电路基于负阻匹配共源网络结构设计. 根据PHEMT器件的小信号S参数和直流I-V参数，提取出该器件的Modified-Materka FET模型参数，变容二极管由共源-漏晶体管来完成，并通过栅压来控制其容值. 测试该电路振荡频率为30.12GHz，输出功率达到12.5dBm,调谐带宽大于150MHz. 振荡器的测试结果与理论设计结果基本吻合     

低电压CMOS压控振荡器设计

设计和分析了一种低电压CMOS压控振荡器,对设计的电路进行理论分析和模型建立,并使用仿真工具对电路进行验证和优化。设计中主要考虑相位噪声和调谐宽度等指标,通过采用电感电容滤波技术以及合理调整电路结构和元器件参数,使相位噪声和调谐宽度均达到了较高的性能指标。结果表明,在1.2 V工作电压下,设计的VCO的尾电流为3 mA,输出振荡频率为2.24~2.57 GHz,中心频率约为2.4 GHz,调谐范围达到13.7%。     

压控振荡器在射频通信电路中的应用

随着现代通信系统和现代雷达系统的出现,射频电路需要在特定的载波频率点上建立稳定的谐波振荡,以便为调制和混额创造必要的条件.设计了一个振荡频率在1.14～1.18 GHz的负阻LC压控振荡器,实现了压控振荡器的宽调频,使频率范围达到加MHz.并且为避免在外部电路对压控振荡器(VCO)的影响,在电路中加入射极跟随器作为buffer,起到阻抗变换和级间隔离的作用.为负阻LC压控振荡器的设计提供了一种参考电路.     

小型化低相噪FBAR压控振荡器的研制

利用薄膜声体波谐振器(FBAR),结合GaAs异质结双极晶体管(HBT)工艺研制了一款小型化低相噪FBAR压控振荡器。将振荡三极管、偏置电路及隔离缓冲放大器集成到一个GaAs单片微波集成电路(MMIC)中,振荡管基极接薄膜电感形成负阻,发射极通过键合线与FBAR进行互连。将GaAs单片集成电路的大信号模型作为一个非线性器件,用探针台测试FBAR谐振器的单端口S参数,导入ADS软件进行谐波平衡法仿真和优化;通过电路制作和调试,达到了预期设计目标。该FBAR压控振荡器中心频率为2.44 GHz,调谐带宽15 MHz,单边带相位噪声达-110 dBc/Hz@10 kHz,与同频段同轴介质压控振荡器指标相当,但其尺寸更小,仅为5 mm×7 mm×2.35 mm。     

三级Colpitts微波混沌振荡器的仿真研究

提出一种具有3级结构的微波Colpitts混沌振荡器,这种新的结构通过增加共基极组态的三极管抑制了电路中三极管寄生电容的负面影响,以提高微波Colpitts混沌振荡器的基本振荡频率和频带宽度。借助Matlab和HSPICE软件对新结构的理想非线性动力学模型和电路进行了时域和频域分析。选用截止频率为9 GHz的三极管时,模型的电路仿真结果表明,新结构的基本振荡频率可达到4.9 GHz;信号的频谱分布更为均匀平坦,10 dB带宽可以达到4.9 GHz。     

基于滤波器和忆阻二极管桥的振荡器实验方案与验证

非线性普遍存在于实际电路中。本文基于Sallen-Key滤波器和忆阻二极管桥设计了一类忆阻振荡器电路。并以一个忆阻振荡器为例，制定了实验方案，完成了实验验证。结果表明，通过改变电路元件参数值，可观测到周期极限环、准周期振荡以及混沌振荡等非线性现象。该电路结构简单，调试方便，现象丰富。该实验方案可作为本科课程设计的重要研究性内容，加深学生对电路中非线性现象的理解。     

交叉耦合混沌信号源电路建模与设计

提出一种交叉耦合结构混沌信号源电路,通过建立非线性混沌模型证明交叉耦合电路满足混沌振荡的条件。将电路拆分成2个互补的两级混沌电路,基于左右两边互补特性分析了交叉耦合混沌电路稳定性提升的机制。通过改变输出端口阻抗,对混沌吸引子和输出信号频谱进行仿真和测试,结果表明：交叉耦合混沌电路维持稳定混沌状态的输出端口阻抗由常规混沌电路的500Ω以上降为80Ω以下,稳定性提升6倍以上;输出混沌信号频谱分三段覆盖1.5～11.4 GHz频段,较常规电路提升50%以上。     

E-Band Active Q-Enhanced Pseudo-combline Resonator in 130 nm SiGe BiCMOS

We present an active Q-enhanced pseudo-combline resonator integrated in 130 nm SiGe BiCMOS. It is shown that the resonator Q₀ can be enhanced, controllably, from 15 to 1578 at 78.8 GHz through application of a SiGe HBT-based negative resistance circuit. This is the first time that resonator Q-enhancement is demonstrated experimentally in silicon above 40 GHz, and the first time negative enhancement with single-ended pseudo-combline loading is used.     

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (C_in) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm², i.e. 0.315 mm².     

A K-Band High-Gain Down-Conversion Mixer in 0.18 $mu$m CMOS Technology

A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of -11 dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively.     

一款应用于多频带的基于新型Cascode有源电感的高Q带通滤波器

设计了一款基于新型Cascode有源电感和有源负阻电路的二阶差分有源带通滤波器。新型有源电感和有源负阻电路的采用可实现在滤波器Q值不变的条件下对滤波器的中心频率进行调节。仿真结果表明,通过调节有源电感和有源负阻电路的偏置条件,可有效增大滤波器的Q值,且在保持Q值恒定在226的条件下中心频率的变化范围为0.2-3.7GHz。滤波器的以上特性使其能很好地应用于多频带的无线系统。     

A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 $mu$m CMOS Technology

By combining an appropriate differential-sensing scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the negative impedance compensation is employed to enhance the gain-bandwidth product. The IC is shown to be tolerant of ESD protection circuit with 0.5 pF equivalent capacitance at the differential inputs. While connected to an InGaAs PIN photodiode exhibiting 0.8 pF equivalent capacitance, the implemented IC has achieved a differential transimpedance gain of 3.5 kOmega and a -3 dB bandwidth of 1.72 GHz. At a data rate of 3 Gb/s, the measured dynamic range is from -20 dBm to +0 dBm at a bit-error rate of 10^-12 with a 2³¹ -1 pseudorandom test pattern. The negative impedance compensation is shown to achieve enhancement factors of 4.5 dB and 520%, respectively, for transimpedance gain and - 3 dB bandwidth. The IC totally consumes 40 mW from a 1.8 V supply.     

Improved chaotic Colpitts oscillator for ultrahigh frequencies

A novel version of the Colpitts oscillator is presented generating chaotic oscillations at gigahertz frequencies. In contrast to the standard oscillator the inductor is moved from the collector circuit of the transistor to the base circuit. PSpice simulations demonstrate chaos at the fundamental frequencies of 0.5, 1 and 2 GHz employing transistors with a threshold frequency of 9 GHz.     

Two-stage chaotic Colpitts oscillator

A novel version of the chaotic Colpitts oscillator is proposed. It contains two bipolar junction transistors coupled in series. The resonance loop consists of an inductor and three capacitors. The two-stage oscillator, compared with the classical circuit, enables the fundamental frequency of chaotic oscillations to be increased by a factor of three. The PSpice simulations performed with 9 GHz threshold frequency transistors demonstrate that the highest fundamental frequencies of chaotic behaviour are 1 and 3 GHz for the classical and the two-stage Colpitts oscillator, respectively     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

Simulation and experimental study of chaos generation in microwave band using Colpitts circuit

Chaotic Colpitts circuits with fundamental frequency f^＊ beyond 1GHz are studied by both circuit simulation and experiment using Philips＇ broadband transistor with threshold frequency of 25GHz. For the basic configuration of Colpitts circuit with f^＊ of about 1,6GHz, broadband continuous power spectra could be obtained from both circuit simulations and experiments. The harmonics of the observed signal from Agilent PSA/ESA spectrum analyzer are as noticeable as far as 12GHz. A modified Colpitts circuit structure employing the parasitic inductance of BJT （Bipolar Junction Transistor） is also proposed and investigated. By circuit simulation, chaotic attractor and broadband continuous power spectra could be obtained from the modified Colpitts circuit with f^＊ of about 3.5GHz. Because the parasitic effects of the prototype board, the experiment result of the modified Colpitts circuit does not agree well with the simulation result. The gap between the simulation and experimental result could be bridged by replacing the lumped circuit elements with distributed ones.